13a0322957
All of the OMAP3 IVA physical address macros in plat-omap/include/plat/omap34xx.h are wrong[1]: OMAP34XX_IVA_INTC_BASE: The IVA interrupt controller does not appear to be accessible from the L3 interconnect, and in any case is definitely not at 0x40000000; the latter address appears to be the internal IVA physical address base for the OMAP2420's interrupt control[2]. OMAP34XX_DSP_BASE: The section of L3 physical address space mapped to the IVA starts at 0x5c000000, not 0x58000000. OMAP34XX_DSP_MEM_BASE: It's not clear what this refers to, but it's not in the L3 IVA address space. OMAP34XX_DSP_IPI_BASE: The Intrusive Port Interface is a relic from the OMAP2420 days and no longer applies to OMAP3. OMAP34XX_DSP_MMU_BASE: The DSP MMU is mapped at 0x5d000000, not 0x5a000000. Nothing that uses these can possibly be working, so drop them. When future code needs these, correct versions can be added in. 1. OMAP34xx Multimedia Device Silicon Revision 3.1.x Rev. W, Table 2-8: "L3 Interconnect View of the IVA2.2 Subsystem Memory Space." p. 229. 2. OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (Rev. Q), section 2.2.4.1, "IVA Memory Space Seen by L3", p. 132. 3. ibid., section 4.3.11, "DSP IPI Overview", p. 200. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
86 lines
3.5 KiB
C
86 lines
3.5 KiB
C
/*
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* arch/arm/plat-omap/include/mach/omap34xx.h
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*
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* This file contains the processor specific definitions of the TI OMAP34XX.
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*
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* Copyright (C) 2007 Texas Instruments.
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* Copyright (C) 2007 Nokia Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_OMAP34XX_H
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#define __ASM_ARCH_OMAP34XX_H
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/*
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* Please place only base defines here and put the rest in device
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* specific headers.
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*/
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#define L4_34XX_BASE 0x48000000
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#define L4_WK_34XX_BASE 0x48300000
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#define L4_PER_34XX_BASE 0x49000000
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#define L4_EMU_34XX_BASE 0x54000000
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#define L3_34XX_BASE 0x68000000
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#define OMAP3430_32KSYNCT_BASE 0x48320000
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#define OMAP3430_CM_BASE 0x48004800
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#define OMAP3430_PRM_BASE 0x48306800
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#define OMAP343X_SMS_BASE 0x6C000000
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#define OMAP343X_SDRC_BASE 0x6D000000
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#define OMAP34XX_GPMC_BASE 0x6E000000
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#define OMAP343X_SCM_BASE 0x48002000
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#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
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#define OMAP34XX_IC_BASE 0x48200000
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#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
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#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
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#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
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#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
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#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
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#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
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#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
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#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
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#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
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#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
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#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
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#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
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#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
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#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
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#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
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#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
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#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
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#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
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#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
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#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
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#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
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#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
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#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
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#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
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#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
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#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
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#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
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#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
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#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
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#define OMAP34XX_SR1_BASE 0x480C9000
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#define OMAP34XX_SR2_BASE 0x480CB000
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#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
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#endif /* __ASM_ARCH_OMAP34XX_H */
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