f6d2fa7dcb
The OTG devices are only available on i.MX27, so ifdef them out for i.MX21. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
566 lines
12 KiB
C
566 lines
12 KiB
C
/*
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* Author: MontaVista Software, Inc.
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* <source@mvista.com>
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*
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* Based on the OMAP devices.c
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/mmc.h>
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#include "devices.h"
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/*
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* SPI master controller
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*
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* - i.MX1: 2 channel (slighly different register setting)
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* - i.MX21: 2 channel
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* - i.MX27: 3 channel
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*/
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static struct resource mxc_spi_resources0[] = {
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{
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.start = CSPI1_BASE_ADDR,
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.end = CSPI1_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_CSPI1,
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.end = MXC_INT_CSPI1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource mxc_spi_resources1[] = {
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{
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.start = CSPI2_BASE_ADDR,
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.end = CSPI2_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_CSPI2,
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.end = MXC_INT_CSPI2,
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.flags = IORESOURCE_IRQ,
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},
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource mxc_spi_resources2[] = {
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{
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.start = CSPI3_BASE_ADDR,
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.end = CSPI3_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_CSPI3,
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.end = MXC_INT_CSPI3,
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.flags = IORESOURCE_IRQ,
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},
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};
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#endif
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struct platform_device mxc_spi_device0 = {
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.name = "spi_imx",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_spi_resources0),
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.resource = mxc_spi_resources0,
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};
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struct platform_device mxc_spi_device1 = {
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.name = "spi_imx",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxc_spi_resources1),
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.resource = mxc_spi_resources1,
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};
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#ifdef CONFIG_MACH_MX27
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struct platform_device mxc_spi_device2 = {
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.name = "spi_imx",
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.id = 2,
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.num_resources = ARRAY_SIZE(mxc_spi_resources2),
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.resource = mxc_spi_resources2,
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};
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#endif
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/*
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* General Purpose Timer
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* - i.MX21: 3 timers
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* - i.MX27: 6 timers
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*/
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/* We use gpt0 as system timer, so do not add a device for this one */
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static struct resource timer1_resources[] = {
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{
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.start = GPT2_BASE_ADDR,
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.end = GPT2_BASE_ADDR + 0x17,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_GPT2,
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.end = MXC_INT_GPT2,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_gpt1 = {
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.name = "imx_gpt",
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.id = 1,
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.num_resources = ARRAY_SIZE(timer1_resources),
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.resource = timer1_resources,
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};
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static struct resource timer2_resources[] = {
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{
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.start = GPT3_BASE_ADDR,
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.end = GPT3_BASE_ADDR + 0x17,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_GPT3,
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.end = MXC_INT_GPT3,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_gpt2 = {
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.name = "imx_gpt",
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.id = 2,
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.num_resources = ARRAY_SIZE(timer2_resources),
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.resource = timer2_resources,
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource timer3_resources[] = {
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{
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.start = GPT4_BASE_ADDR,
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.end = GPT4_BASE_ADDR + 0x17,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_GPT4,
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.end = MXC_INT_GPT4,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_gpt3 = {
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.name = "imx_gpt",
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.id = 3,
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.num_resources = ARRAY_SIZE(timer3_resources),
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.resource = timer3_resources,
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};
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static struct resource timer4_resources[] = {
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{
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.start = GPT5_BASE_ADDR,
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.end = GPT5_BASE_ADDR + 0x17,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_GPT5,
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.end = MXC_INT_GPT5,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_gpt4 = {
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.name = "imx_gpt",
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.id = 4,
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.num_resources = ARRAY_SIZE(timer4_resources),
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.resource = timer4_resources,
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};
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static struct resource timer5_resources[] = {
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{
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.start = GPT6_BASE_ADDR,
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.end = GPT6_BASE_ADDR + 0x17,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_GPT6,
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.end = MXC_INT_GPT6,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_gpt5 = {
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.name = "imx_gpt",
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.id = 5,
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.num_resources = ARRAY_SIZE(timer5_resources),
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.resource = timer5_resources,
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};
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#endif
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/*
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* Watchdog:
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* - i.MX1
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* - i.MX21
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* - i.MX27
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*/
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static struct resource mxc_wdt_resources[] = {
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{
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.start = WDOG_BASE_ADDR,
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.end = WDOG_BASE_ADDR + 0x30,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_wdt = {
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.name = "mxc_wdt",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_wdt_resources),
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.resource = mxc_wdt_resources,
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};
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static struct resource mxc_w1_master_resources[] = {
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{
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.start = OWIRE_BASE_ADDR,
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.end = OWIRE_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_w1_master_device = {
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.name = "mxc_w1",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
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.resource = mxc_w1_master_resources,
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};
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static struct resource mxc_nand_resources[] = {
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{
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.start = NFC_BASE_ADDR,
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.end = NFC_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_NANDFC,
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.end = MXC_INT_NANDFC,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_nand_device = {
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.name = "mxc_nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_nand_resources),
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.resource = mxc_nand_resources,
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};
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/*
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* lcdc:
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* - i.MX1: the basic controller
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* - i.MX21: to be checked
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* - i.MX27: like i.MX1, with slightly variations
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*/
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static struct resource mxc_fb[] = {
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{
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.start = LCDC_BASE_ADDR,
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.end = LCDC_BASE_ADDR + 0xFFF,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_LCDC,
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.end = MXC_INT_LCDC,
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.flags = IORESOURCE_IRQ,
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}
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};
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/* mxc lcd driver */
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struct platform_device mxc_fb_device = {
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.name = "imx-fb",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fb),
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.resource = mxc_fb,
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.dev = {
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.coherent_dma_mask = 0xFFFFFFFF,
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},
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource mxc_fec_resources[] = {
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{
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.start = FEC_BASE_ADDR,
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.end = FEC_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_FEC,
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.end = MXC_INT_FEC,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_fec_device = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fec_resources),
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.resource = mxc_fec_resources,
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};
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#endif
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static struct resource mxc_i2c_1_resources[] = {
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{
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.start = I2C_BASE_ADDR,
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.end = I2C_BASE_ADDR + 0x0fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_I2C,
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.end = MXC_INT_I2C,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_i2c_device0 = {
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.name = "imx-i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
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.resource = mxc_i2c_1_resources,
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource mxc_i2c_2_resources[] = {
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{
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.start = I2C2_BASE_ADDR,
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.end = I2C2_BASE_ADDR + 0x0fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_I2C2,
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.end = MXC_INT_I2C2,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_i2c_device1 = {
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.name = "imx-i2c",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
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.resource = mxc_i2c_2_resources,
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};
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#endif
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static struct resource mxc_pwm_resources[] = {
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{
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.start = PWM_BASE_ADDR,
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.end = PWM_BASE_ADDR + 0x0fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_PWM,
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.end = MXC_INT_PWM,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_pwm_device = {
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.name = "mxc_pwm",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_pwm_resources),
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.resource = mxc_pwm_resources,
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};
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/*
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* Resource definition for the MXC SDHC
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*/
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static struct resource mxc_sdhc1_resources[] = {
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{
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.start = SDHC1_BASE_ADDR,
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.end = SDHC1_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_SDHC1,
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.end = MXC_INT_SDHC1,
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.flags = IORESOURCE_IRQ,
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}, {
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.start = DMA_REQ_SDHC1,
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.end = DMA_REQ_SDHC1,
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.flags = IORESOURCE_DMA,
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},
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};
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static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
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struct platform_device mxc_sdhc_device0 = {
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.name = "mxc-mmc",
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.id = 0,
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.dev = {
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.dma_mask = &mxc_sdhc1_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
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.resource = mxc_sdhc1_resources,
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};
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static struct resource mxc_sdhc2_resources[] = {
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{
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.start = SDHC2_BASE_ADDR,
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.end = SDHC2_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_SDHC2,
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.end = MXC_INT_SDHC2,
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.flags = IORESOURCE_IRQ,
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}, {
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.start = DMA_REQ_SDHC2,
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.end = DMA_REQ_SDHC2,
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.flags = IORESOURCE_DMA,
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},
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};
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static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
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struct platform_device mxc_sdhc_device1 = {
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.name = "mxc-mmc",
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.id = 1,
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.dev = {
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.dma_mask = &mxc_sdhc2_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
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.resource = mxc_sdhc2_resources,
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource otg_resources[] = {
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{
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.start = OTG_BASE_ADDR,
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.end = OTG_BASE_ADDR + 0x1ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_USB3,
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.end = MXC_INT_USB3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 otg_dmamask = 0xffffffffUL;
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/* OTG gadget device */
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struct platform_device mxc_otg_udc_device = {
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.name = "fsl-usb2-udc",
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.id = -1,
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.dev = {
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.dma_mask = &otg_dmamask,
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.coherent_dma_mask = 0xffffffffUL,
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},
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.resource = otg_resources,
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.num_resources = ARRAY_SIZE(otg_resources),
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};
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/* OTG host */
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struct platform_device mxc_otg_host = {
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.name = "mxc-ehci",
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.id = 0,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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.dma_mask = &otg_dmamask,
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},
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.resource = otg_resources,
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.num_resources = ARRAY_SIZE(otg_resources),
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};
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/* USB host 1 */
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static u64 usbh1_dmamask = 0xffffffffUL;
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static struct resource mxc_usbh1_resources[] = {
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{
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.start = OTG_BASE_ADDR + 0x200,
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.end = OTG_BASE_ADDR + 0x3ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_USB1,
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.end = MXC_INT_USB1,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_usbh1 = {
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.name = "mxc-ehci",
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.id = 1,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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.dma_mask = &usbh1_dmamask,
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},
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.resource = mxc_usbh1_resources,
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.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
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};
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/* USB host 2 */
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static u64 usbh2_dmamask = 0xffffffffUL;
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static struct resource mxc_usbh2_resources[] = {
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{
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.start = OTG_BASE_ADDR + 0x400,
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.end = OTG_BASE_ADDR + 0x5ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_USB2,
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.end = MXC_INT_USB2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_usbh2 = {
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.name = "mxc-ehci",
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.id = 2,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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.dma_mask = &usbh2_dmamask,
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},
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.resource = mxc_usbh2_resources,
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|
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
|
|
};
|
|
#endif
|
|
|
|
/* GPIO port description */
|
|
static struct mxc_gpio_port imx_gpio_ports[] = {
|
|
{
|
|
.chip.label = "gpio-0",
|
|
.irq = MXC_INT_GPIO,
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START,
|
|
}, {
|
|
.chip.label = "gpio-1",
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
|
|
}, {
|
|
.chip.label = "gpio-2",
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
|
|
}, {
|
|
.chip.label = "gpio-3",
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
|
|
}, {
|
|
.chip.label = "gpio-4",
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
|
|
}, {
|
|
.chip.label = "gpio-5",
|
|
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
|
|
.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
|
|
}
|
|
};
|
|
|
|
int __init mxc_register_gpios(void)
|
|
{
|
|
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
|
|
}
|