895d603f94
On Freescale parts with multiple MSI controllers, the controllers are combined into one "pool" of interrupts. Whenever a device requests an MSI interrupt, the next available interrupt from the pool is selected, regardless of which MSI controller the interrupt is from. This works because each PCI bus has an ATMU to all of CCSR, so any PCI device can access any MSI interrupt register. The fsl,msi property is used to specify that a given PCI bus should only use a specific MSI device. This is necessary, for example, with the Freescale hypervisor, because the MSI devices are assigned to specific partitions. Ideally, we'd like to be able to assign MSI devices to PCI busses within the MSI or PCI layers. However, there does not appear to be a mechanism to do that. Whenever the MSI layer wants to allocate an MSI interrupt to a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we could register an MSI device with a specific PCI bus. So instead we remember the phandles of each MSI device, and we use that to limit our search for an available interrupt. Whenever we are asked to allocate a new interrupt for a PCI device, we check the fsl,msi property of the PCI bus for that device. If it exists, then as we are looping over all MSI devices, we skip the ones that don't have a matching phandle. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/*
|
|
* Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
|
|
*
|
|
* Author: Tony Li <tony.li@freescale.com>
|
|
* Jason Jin <Jason.jin@freescale.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; version 2 of the
|
|
* License.
|
|
*
|
|
*/
|
|
#ifndef _POWERPC_SYSDEV_FSL_MSI_H
|
|
#define _POWERPC_SYSDEV_FSL_MSI_H
|
|
|
|
#include <linux/of.h>
|
|
#include <asm/msi_bitmap.h>
|
|
|
|
#define NR_MSI_REG 8
|
|
#define IRQS_PER_MSI_REG 32
|
|
#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
|
|
|
|
#define FSL_PIC_IP_MASK 0x0000000F
|
|
#define FSL_PIC_IP_MPIC 0x00000001
|
|
#define FSL_PIC_IP_IPIC 0x00000002
|
|
|
|
struct fsl_msi {
|
|
struct irq_host *irqhost;
|
|
|
|
unsigned long cascade_irq;
|
|
|
|
u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
|
|
void __iomem *msi_regs;
|
|
u32 feature;
|
|
int msi_virqs[NR_MSI_REG];
|
|
|
|
struct msi_bitmap bitmap;
|
|
|
|
struct list_head list; /* support multiple MSI banks */
|
|
|
|
phandle phandle;
|
|
};
|
|
|
|
#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
|
|
|