99a70aa051
Signed-off-by: Richard Kuo <rkuo@codeaurora.org> Signed-off-by: Linas Vepstas <linas@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/*
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* System level definitions for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <asm/atomic.h>
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#include <asm/hexagon_vm.h>
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struct thread_struct;
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extern struct task_struct *__switch_to(struct task_struct *,
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struct task_struct *,
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struct task_struct *);
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#define switch_to(p, n, r) do {\
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r = __switch_to((p), (n), (r));\
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} while (0)
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#define rmb() barrier()
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#define read_barrier_depends() barrier()
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#define wmb() barrier()
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#define mb() barrier()
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#define smp_rmb() barrier()
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#define smp_read_barrier_depends() barrier()
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#define smp_wmb() barrier()
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#define smp_mb() barrier()
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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/*
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* __xchg - atomically exchange a register and a memory location
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* @x: value to swap
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* @ptr: pointer to memory
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* @size: size of the value
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*
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* Only 4 bytes supported currently.
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*
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* Note: there was an errata for V2 about .new's and memw_locked.
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*
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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unsigned long retval;
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/* Can't seem to use printk or panic here, so just stop */
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if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
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__asm__ __volatile__ (
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"1: %0 = memw_locked(%1);\n" /* load into retval */
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" memw_locked(%1,P0) = %2;\n" /* store into memory */
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" if !P0 jump 1b;\n"
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: "=&r" (retval)
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: "r" (ptr), "r" (x)
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: "memory", "p0"
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);
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return retval;
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}
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/*
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* Atomically swap the contents of a register with memory. Should be atomic
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* between multiple CPU's and within interrupts on the same CPU.
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*/
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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/* Set a value and use a memory barrier. Used by the scheduler somewhere. */
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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/*
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* see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
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* looks just like atomic_cmpxchg on our arch currently with a bunch of
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* variable casting.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr, old, new) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __oldval = 0; \
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\
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asm volatile( \
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"1: %0 = memw_locked(%1);\n" \
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" { P0 = cmp.eq(%0,%2);\n" \
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" if (!P0.new) jump:nt 2f; }\n" \
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" memw_locked(%1,p0) = %3;\n" \
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" if (!P0) jump 1b;\n" \
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"2:\n" \
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: "=&r" (__oldval) \
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: "r" (__ptr), "r" (__old), "r" (__new) \
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: "memory", "p0" \
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); \
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__oldval; \
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})
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/* Should probably shoot for an 8-byte aligned stack pointer */
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#define STACK_MASK (~7)
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#define arch_align_stack(x) (x & STACK_MASK)
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#endif
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