856 lines
19 KiB
Text
856 lines
19 KiB
Text
/* fuc microcode for nvc0 PGRAPH/HUB
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*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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/* To build:
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* m4 nvc0_grhub.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grhub.fuc.h
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*/
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.section #nvc0_grhub_data
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include(`nvc0_graph.fuc')
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gpc_count: .b32 0
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rop_count: .b32 0
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cmd_queue: queue_init
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hub_mmio_list_head: .b32 0
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hub_mmio_list_tail: .b32 0
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ctx_current: .b32 0
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chipsets:
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.b8 0xc0 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xc1 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc1_hub_mmio_tail
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.b8 0xc3 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xc4 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xc8 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xce 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xcf 0 0 0
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.b16 #nvc0_hub_mmio_head
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.b16 #nvc0_hub_mmio_tail
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.b8 0xd9 0 0 0
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.b16 #nvd9_hub_mmio_head
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.b16 #nvd9_hub_mmio_tail
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.b8 0 0 0 0
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nvc0_hub_mmio_head:
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mmctx_data(0x17e91c, 2)
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mmctx_data(0x400204, 2)
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mmctx_data(0x404004, 11)
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mmctx_data(0x404044, 1)
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mmctx_data(0x404094, 14)
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mmctx_data(0x4040d0, 7)
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mmctx_data(0x4040f8, 1)
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mmctx_data(0x404130, 3)
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mmctx_data(0x404150, 3)
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mmctx_data(0x404164, 2)
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mmctx_data(0x404174, 3)
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mmctx_data(0x404200, 8)
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mmctx_data(0x404404, 14)
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mmctx_data(0x404460, 4)
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mmctx_data(0x404480, 1)
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mmctx_data(0x404498, 1)
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mmctx_data(0x404604, 4)
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mmctx_data(0x404618, 32)
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mmctx_data(0x404698, 21)
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mmctx_data(0x4046f0, 2)
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mmctx_data(0x404700, 22)
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mmctx_data(0x405800, 1)
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mmctx_data(0x405830, 3)
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mmctx_data(0x405854, 1)
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mmctx_data(0x405870, 4)
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mmctx_data(0x405a00, 2)
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mmctx_data(0x405a18, 1)
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mmctx_data(0x406020, 1)
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mmctx_data(0x406028, 4)
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mmctx_data(0x4064a8, 2)
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mmctx_data(0x4064b4, 2)
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mmctx_data(0x407804, 1)
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mmctx_data(0x40780c, 6)
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mmctx_data(0x4078bc, 1)
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mmctx_data(0x408000, 7)
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mmctx_data(0x408064, 1)
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mmctx_data(0x408800, 3)
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mmctx_data(0x408900, 4)
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mmctx_data(0x408980, 1)
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nvc0_hub_mmio_tail:
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mmctx_data(0x4064c0, 2)
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nvc1_hub_mmio_tail:
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nvd9_hub_mmio_head:
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mmctx_data(0x17e91c, 2)
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mmctx_data(0x400204, 2)
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mmctx_data(0x404004, 10)
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mmctx_data(0x404044, 1)
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mmctx_data(0x404094, 14)
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mmctx_data(0x4040d0, 7)
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mmctx_data(0x4040f8, 1)
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mmctx_data(0x404130, 3)
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mmctx_data(0x404150, 3)
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mmctx_data(0x404164, 2)
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mmctx_data(0x404178, 2)
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mmctx_data(0x404200, 8)
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mmctx_data(0x404404, 14)
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mmctx_data(0x404460, 4)
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mmctx_data(0x404480, 1)
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mmctx_data(0x404498, 1)
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mmctx_data(0x404604, 4)
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mmctx_data(0x404618, 32)
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mmctx_data(0x404698, 21)
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mmctx_data(0x4046f0, 2)
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mmctx_data(0x404700, 22)
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mmctx_data(0x405800, 1)
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mmctx_data(0x405830, 3)
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mmctx_data(0x405854, 1)
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mmctx_data(0x405870, 4)
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mmctx_data(0x405a00, 2)
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mmctx_data(0x405a18, 1)
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mmctx_data(0x406020, 1)
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mmctx_data(0x406028, 4)
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mmctx_data(0x4064a8, 2)
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mmctx_data(0x4064b4, 5)
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mmctx_data(0x407804, 1)
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mmctx_data(0x40780c, 6)
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mmctx_data(0x4078bc, 1)
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mmctx_data(0x408000, 7)
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mmctx_data(0x408064, 1)
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mmctx_data(0x408800, 3)
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mmctx_data(0x408900, 4)
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mmctx_data(0x408980, 1)
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nvd9_hub_mmio_tail:
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.align 256
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chan_data:
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chan_mmio_count: .b32 0
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chan_mmio_address: .b32 0
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.align 256
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xfer_data: .b32 0
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.section #nvc0_grhub_code
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bra #init
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define(`include_code')
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include(`nvc0_graph.fuc')
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// reports an exception to the host
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//
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// In: $r15 error code (see nvc0_graph.fuc)
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//
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error:
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push $r14
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mov $r14 0x814
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shl b32 $r14 6
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iowr I[$r14 + 0x000] $r15 // CC_SCRATCH[5] = error code
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mov $r14 0xc1c
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shl b32 $r14 6
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mov $r15 1
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iowr I[$r14 + 0x000] $r15 // INTR_UP_SET
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pop $r14
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ret
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// HUB fuc initialisation, executed by triggering ucode start, will
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// fall through to main loop after completion.
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//
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// Input:
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// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
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//
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// Output:
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// CC_SCRATCH[0]:
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// 31:31: set to signal completion
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// CC_SCRATCH[1]:
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// 31:0: total PGRAPH context size
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//
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init:
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clear b32 $r0
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mov $sp $r0
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mov $xdbase $r0
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// enable fifo access
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mov $r1 0x1200
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mov $r2 2
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iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
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// setup i0 handler, and route all interrupts to it
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mov $r1 #ih
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mov $iv0 $r1
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mov $r1 0x400
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iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
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// route HUB_CHANNEL_SWITCH to fuc interrupt 8
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mov $r3 0x404
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shl b32 $r3 6
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mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
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iowr I[$r3 + 0x000] $r2
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// not sure what these are, route them because NVIDIA does, and
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// the IRQ handler will signal the host if we ever get one.. we
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// may find out if/why we need to handle these if so..
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//
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mov $r2 0x2004
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iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
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mov $r2 0x200b
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iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
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mov $r2 0x200c
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iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
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// enable all INTR_UP interrupts
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mov $r2 0xc24
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shl b32 $r2 6
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not b32 $r3 $r0
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iowr I[$r2] $r3
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// enable fifo, ctxsw, 9, 10, 15 interrupts
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mov $r2 -0x78fc // 0x8704
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sethi $r2 0
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iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
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// fifo level triggered, rest edge
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sub b32 $r1 0x100
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mov $r2 4
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iowr I[$r1] $r2
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// enable interrupts
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bset $flags ie0
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// fetch enabled GPC/ROP counts
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mov $r14 -0x69fc // 0x409604
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sethi $r14 0x400000
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call #nv_rd32
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extr $r1 $r15 16:20
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st b32 D[$r0 + #rop_count] $r1
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and $r15 0x1f
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st b32 D[$r0 + #gpc_count] $r15
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// set BAR_REQMASK to GPC mask
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mov $r1 1
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shl b32 $r1 $r15
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sub b32 $r1 1
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mov $r2 0x40c
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shl b32 $r2 6
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iowr I[$r2 + 0x000] $r1
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iowr I[$r2 + 0x100] $r1
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// find context data for this chipset
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mov $r2 0x800
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shl b32 $r2 6
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iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
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mov $r15 #chipsets - 8
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init_find_chipset:
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add b32 $r15 8
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ld b32 $r3 D[$r15 + 0x00]
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cmpu b32 $r3 $r2
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bra e #init_context
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cmpu b32 $r3 0
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bra ne #init_find_chipset
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// unknown chipset
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ret
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// context size calculation, reserve first 256 bytes for use by fuc
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init_context:
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mov $r1 256
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// calculate size of mmio context data
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ld b16 $r14 D[$r15 + 4]
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ld b16 $r15 D[$r15 + 6]
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sethi $r14 0
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st b32 D[$r0 + #hub_mmio_list_head] $r14
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st b32 D[$r0 + #hub_mmio_list_tail] $r15
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call #mmctx_size
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// set mmctx base addresses now so we don't have to do it later,
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// they don't (currently) ever change
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mov $r3 0x700
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shl b32 $r3 6
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shr b32 $r4 $r1 8
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iowr I[$r3 + 0x000] $r4 // MMCTX_SAVE_SWBASE
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iowr I[$r3 + 0x100] $r4 // MMCTX_LOAD_SWBASE
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add b32 $r3 0x1300
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add b32 $r1 $r15
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shr b32 $r15 2
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iowr I[$r3 + 0x000] $r15 // MMCTX_LOAD_COUNT, wtf for?!?
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// strands, base offset needs to be aligned to 256 bytes
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shr b32 $r1 8
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add b32 $r1 1
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shl b32 $r1 8
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mov b32 $r15 $r1
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call #strand_ctx_init
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add b32 $r1 $r15
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// initialise each GPC in sequence by passing in the offset of its
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// context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
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// has previously been uploaded by the host) running.
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//
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// the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
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// when it has completed, and return the size of its context data
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// in GPCn_CC_SCRATCH[1]
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//
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ld b32 $r3 D[$r0 + #gpc_count]
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mov $r4 0x2000
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sethi $r4 0x500000
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init_gpc:
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// setup, and start GPC ucode running
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add b32 $r14 $r4 0x804
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mov b32 $r15 $r1
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call #nv_wr32 // CC_SCRATCH[1] = ctx offset
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add b32 $r14 $r4 0x800
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mov b32 $r15 $r2
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call #nv_wr32 // CC_SCRATCH[0] = chipset
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add b32 $r14 $r4 0x10c
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clear b32 $r15
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call #nv_wr32
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add b32 $r14 $r4 0x104
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call #nv_wr32 // ENTRY
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add b32 $r14 $r4 0x100
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mov $r15 2 // CTRL_START_TRIGGER
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call #nv_wr32 // CTRL
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// wait for it to complete, and adjust context size
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add b32 $r14 $r4 0x800
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init_gpc_wait:
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call #nv_rd32
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xbit $r15 $r15 31
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bra e #init_gpc_wait
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add b32 $r14 $r4 0x804
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call #nv_rd32
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add b32 $r1 $r15
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// next!
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add b32 $r4 0x8000
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sub b32 $r3 1
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bra ne #init_gpc
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// save context size, and tell host we're ready
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mov $r2 0x800
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shl b32 $r2 6
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iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size
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add b32 $r2 0x800
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clear b32 $r1
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bset $r1 31
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iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000
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// Main program loop, very simple, sleeps until woken up by the interrupt
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// handler, pulls a command from the queue and executes its handler
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//
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main:
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// sleep until we have something to do
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bset $flags $p0
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sleep $p0
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mov $r13 #cmd_queue
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call #queue_get
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bra $p1 #main
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// context switch, requested by GPU?
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cmpu b32 $r14 0x4001
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bra ne #main_not_ctx_switch
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trace_set(T_AUTO)
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mov $r1 0xb00
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shl b32 $r1 6
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iord $r2 I[$r1 + 0x100] // CHAN_NEXT
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iord $r1 I[$r1 + 0x000] // CHAN_CUR
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xbit $r3 $r1 31
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bra e #chsw_no_prev
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xbit $r3 $r2 31
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bra e #chsw_prev_no_next
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push $r2
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mov b32 $r2 $r1
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trace_set(T_SAVE)
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bclr $flags $p1
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bset $flags $p2
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call #ctx_xfer
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trace_clr(T_SAVE);
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pop $r2
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trace_set(T_LOAD);
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bset $flags $p1
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call #ctx_xfer
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trace_clr(T_LOAD);
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bra #chsw_done
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chsw_prev_no_next:
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push $r2
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mov b32 $r2 $r1
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bclr $flags $p1
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bclr $flags $p2
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call #ctx_xfer
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pop $r2
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mov $r1 0xb00
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shl b32 $r1 6
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iowr I[$r1] $r2
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bra #chsw_done
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chsw_no_prev:
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xbit $r3 $r2 31
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bra e #chsw_done
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bset $flags $p1
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bclr $flags $p2
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call #ctx_xfer
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// ack the context switch request
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chsw_done:
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mov $r1 0xb0c
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shl b32 $r1 6
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mov $r2 1
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iowr I[$r1 + 0x000] $r2 // 0x409b0c
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trace_clr(T_AUTO)
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bra #main
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// request to set current channel? (*not* a context switch)
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main_not_ctx_switch:
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cmpu b32 $r14 0x0001
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bra ne #main_not_ctx_chan
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mov b32 $r2 $r15
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call #ctx_chan
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bra #main_done
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// request to store current channel context?
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main_not_ctx_chan:
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cmpu b32 $r14 0x0002
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bra ne #main_not_ctx_save
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trace_set(T_SAVE)
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bclr $flags $p1
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bclr $flags $p2
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call #ctx_xfer
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trace_clr(T_SAVE)
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bra #main_done
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main_not_ctx_save:
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shl b32 $r15 $r14 16
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or $r15 E_BAD_COMMAND
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call #error
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bra #main
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main_done:
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mov $r1 0x820
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shl b32 $r1 6
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clear b32 $r2
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bset $r2 31
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iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
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bra #main
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// interrupt handler
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ih:
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push $r8
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mov $r8 $flags
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push $r8
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push $r9
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push $r10
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push $r11
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push $r13
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push $r14
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push $r15
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// incoming fifo command?
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iord $r10 I[$r0 + 0x200] // INTR
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|
and $r11 $r10 0x00000004
|
|
bra e #ih_no_fifo
|
|
// queue incoming fifo command for later processing
|
|
mov $r11 0x1900
|
|
mov $r13 #cmd_queue
|
|
iord $r14 I[$r11 + 0x100] // FIFO_CMD
|
|
iord $r15 I[$r11 + 0x000] // FIFO_DATA
|
|
call #queue_put
|
|
add b32 $r11 0x400
|
|
mov $r14 1
|
|
iowr I[$r11 + 0x000] $r14 // FIFO_ACK
|
|
|
|
// context switch request?
|
|
ih_no_fifo:
|
|
and $r11 $r10 0x00000100
|
|
bra e #ih_no_ctxsw
|
|
// enqueue a context switch for later processing
|
|
mov $r13 #cmd_queue
|
|
mov $r14 0x4001
|
|
call #queue_put
|
|
|
|
// anything we didn't handle, bring it to the host's attention
|
|
ih_no_ctxsw:
|
|
mov $r11 0x104
|
|
not b32 $r11
|
|
and $r11 $r10 $r11
|
|
bra e #ih_no_other
|
|
mov $r10 0xc1c
|
|
shl b32 $r10 6
|
|
iowr I[$r10] $r11 // INTR_UP_SET
|
|
|
|
// ack, and wake up main()
|
|
ih_no_other:
|
|
iowr I[$r0 + 0x100] $r10 // INTR_ACK
|
|
|
|
pop $r15
|
|
pop $r14
|
|
pop $r13
|
|
pop $r11
|
|
pop $r10
|
|
pop $r9
|
|
pop $r8
|
|
mov $flags $r8
|
|
pop $r8
|
|
bclr $flags $p0
|
|
iret
|
|
|
|
// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
|
|
ctx_4160s:
|
|
mov $r14 0x4160
|
|
sethi $r14 0x400000
|
|
mov $r15 1
|
|
call #nv_wr32
|
|
ctx_4160s_wait:
|
|
call #nv_rd32
|
|
xbit $r15 $r15 4
|
|
bra e #ctx_4160s_wait
|
|
ret
|
|
|
|
// Without clearing again at end of xfer, some things cause PGRAPH
|
|
// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
|
|
// still function with it set however...
|
|
ctx_4160c:
|
|
mov $r14 0x4160
|
|
sethi $r14 0x400000
|
|
clear b32 $r15
|
|
call #nv_wr32
|
|
ret
|
|
|
|
// Again, not real sure
|
|
//
|
|
// In: $r15 value to set 0x404170 to
|
|
//
|
|
ctx_4170s:
|
|
mov $r14 0x4170
|
|
sethi $r14 0x400000
|
|
or $r15 0x10
|
|
call #nv_wr32
|
|
ret
|
|
|
|
// Waits for a ctx_4170s() call to complete
|
|
//
|
|
ctx_4170w:
|
|
mov $r14 0x4170
|
|
sethi $r14 0x400000
|
|
call #nv_rd32
|
|
and $r15 0x10
|
|
bra ne #ctx_4170w
|
|
ret
|
|
|
|
// Disables various things, waits a bit, and re-enables them..
|
|
//
|
|
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
|
|
// good description for the bits we turn off? Anyways, without this,
|
|
// funny things happen.
|
|
//
|
|
ctx_redswitch:
|
|
mov $r14 0x614
|
|
shl b32 $r14 6
|
|
mov $r15 0x270
|
|
iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
|
|
mov $r15 8
|
|
ctx_redswitch_delay:
|
|
sub b32 $r15 1
|
|
bra ne #ctx_redswitch_delay
|
|
mov $r15 0x770
|
|
iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
|
|
ret
|
|
|
|
// Not a clue what this is for, except that unless the value is 0x10, the
|
|
// strand context is saved (and presumably restored) incorrectly..
|
|
//
|
|
// In: $r15 value to set to (0x00/0x10 are used)
|
|
//
|
|
ctx_86c:
|
|
mov $r14 0x86c
|
|
shl b32 $r14 6
|
|
iowr I[$r14] $r15 // HUB(0x86c) = val
|
|
mov $r14 -0x75ec
|
|
sethi $r14 0x400000
|
|
call #nv_wr32 // ROP(0xa14) = val
|
|
mov $r14 -0x5794
|
|
sethi $r14 0x410000
|
|
call #nv_wr32 // GPC(0x86c) = val
|
|
ret
|
|
|
|
// ctx_load - load's a channel's ctxctl data, and selects its vm
|
|
//
|
|
// In: $r2 channel address
|
|
//
|
|
ctx_load:
|
|
trace_set(T_CHAN)
|
|
|
|
// switch to channel, somewhat magic in parts..
|
|
mov $r10 12 // DONE_UNK12
|
|
call #wait_donez
|
|
mov $r1 0xa24
|
|
shl b32 $r1 6
|
|
iowr I[$r1 + 0x000] $r0 // 0x409a24
|
|
mov $r3 0xb00
|
|
shl b32 $r3 6
|
|
iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
|
|
mov $r1 0xa0c
|
|
shl b32 $r1 6
|
|
mov $r4 7
|
|
iowr I[$r1 + 0x000] $r2 // MEM_CHAN
|
|
iowr I[$r1 + 0x100] $r4 // MEM_CMD
|
|
ctx_chan_wait_0:
|
|
iord $r4 I[$r1 + 0x100]
|
|
and $r4 0x1f
|
|
bra ne #ctx_chan_wait_0
|
|
iowr I[$r3 + 0x000] $r2 // CHAN_CUR
|
|
|
|
// load channel header, fetch PGRAPH context pointer
|
|
mov $xtargets $r0
|
|
bclr $r2 31
|
|
shl b32 $r2 4
|
|
add b32 $r2 2
|
|
|
|
trace_set(T_LCHAN)
|
|
mov $r1 0xa04
|
|
shl b32 $r1 6
|
|
iowr I[$r1 + 0x000] $r2 // MEM_BASE
|
|
mov $r1 0xa20
|
|
shl b32 $r1 6
|
|
mov $r2 0x0002
|
|
sethi $r2 0x80000000
|
|
iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
|
|
mov $r1 0x10 // chan + 0x0210
|
|
mov $r2 #xfer_data
|
|
sethi $r2 0x00020000 // 16 bytes
|
|
xdld $r1 $r2
|
|
xdwait
|
|
trace_clr(T_LCHAN)
|
|
|
|
// update current context
|
|
ld b32 $r1 D[$r0 + #xfer_data + 4]
|
|
shl b32 $r1 24
|
|
ld b32 $r2 D[$r0 + #xfer_data + 0]
|
|
shr b32 $r2 8
|
|
or $r1 $r2
|
|
st b32 D[$r0 + #ctx_current] $r1
|
|
|
|
// set transfer base to start of context, and fetch context header
|
|
trace_set(T_LCTXH)
|
|
mov $r2 0xa04
|
|
shl b32 $r2 6
|
|
iowr I[$r2 + 0x000] $r1 // MEM_BASE
|
|
mov $r2 1
|
|
mov $r1 0xa20
|
|
shl b32 $r1 6
|
|
iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
|
|
mov $r1 #chan_data
|
|
sethi $r1 0x00060000 // 256 bytes
|
|
xdld $r0 $r1
|
|
xdwait
|
|
trace_clr(T_LCTXH)
|
|
|
|
trace_clr(T_CHAN)
|
|
ret
|
|
|
|
// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
|
|
// the active channel for ctxctl, but not actually transfer
|
|
// any context data. intended for use only during initial
|
|
// context construction.
|
|
//
|
|
// In: $r2 channel address
|
|
//
|
|
ctx_chan:
|
|
call #ctx_4160s
|
|
call #ctx_load
|
|
mov $r10 12 // DONE_UNK12
|
|
call #wait_donez
|
|
mov $r1 0xa10
|
|
shl b32 $r1 6
|
|
mov $r2 5
|
|
iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???)
|
|
ctx_chan_wait:
|
|
iord $r2 I[$r1 + 0x000]
|
|
or $r2 $r2
|
|
bra ne #ctx_chan_wait
|
|
call #ctx_4160c
|
|
ret
|
|
|
|
// Execute per-context state overrides list
|
|
//
|
|
// Only executed on the first load of a channel. Might want to look into
|
|
// removing this and having the host directly modify the channel's context
|
|
// to change this state... The nouveau DRM already builds this list as
|
|
// it's definitely needed for NVIDIA's, so we may as well use it for now
|
|
//
|
|
// Input: $r1 mmio list length
|
|
//
|
|
ctx_mmio_exec:
|
|
// set transfer base to be the mmio list
|
|
ld b32 $r3 D[$r0 + #chan_mmio_address]
|
|
mov $r2 0xa04
|
|
shl b32 $r2 6
|
|
iowr I[$r2 + 0x000] $r3 // MEM_BASE
|
|
|
|
clear b32 $r3
|
|
ctx_mmio_loop:
|
|
// fetch next 256 bytes of mmio list if necessary
|
|
and $r4 $r3 0xff
|
|
bra ne #ctx_mmio_pull
|
|
mov $r5 #xfer_data
|
|
sethi $r5 0x00060000 // 256 bytes
|
|
xdld $r3 $r5
|
|
xdwait
|
|
|
|
// execute a single list entry
|
|
ctx_mmio_pull:
|
|
ld b32 $r14 D[$r4 + #xfer_data + 0x00]
|
|
ld b32 $r15 D[$r4 + #xfer_data + 0x04]
|
|
call #nv_wr32
|
|
|
|
// next!
|
|
add b32 $r3 8
|
|
sub b32 $r1 1
|
|
bra ne #ctx_mmio_loop
|
|
|
|
// set transfer base back to the current context
|
|
ctx_mmio_done:
|
|
ld b32 $r3 D[$r0 + #ctx_current]
|
|
iowr I[$r2 + 0x000] $r3 // MEM_BASE
|
|
|
|
// disable the mmio list now, we don't need/want to execute it again
|
|
st b32 D[$r0 + #chan_mmio_count] $r0
|
|
mov $r1 #chan_data
|
|
sethi $r1 0x00060000 // 256 bytes
|
|
xdst $r0 $r1
|
|
xdwait
|
|
ret
|
|
|
|
// Transfer HUB context data between GPU and storage area
|
|
//
|
|
// In: $r2 channel address
|
|
// $p1 clear on save, set on load
|
|
// $p2 set if opposite direction done/will be done, so:
|
|
// on save it means: "a load will follow this save"
|
|
// on load it means: "a save preceeded this load"
|
|
//
|
|
ctx_xfer:
|
|
bra not $p1 #ctx_xfer_pre
|
|
bra $p2 #ctx_xfer_pre_load
|
|
ctx_xfer_pre:
|
|
mov $r15 0x10
|
|
call #ctx_86c
|
|
call #ctx_4160s
|
|
bra not $p1 #ctx_xfer_exec
|
|
|
|
ctx_xfer_pre_load:
|
|
mov $r15 2
|
|
call #ctx_4170s
|
|
call #ctx_4170w
|
|
call #ctx_redswitch
|
|
clear b32 $r15
|
|
call #ctx_4170s
|
|
call #ctx_load
|
|
|
|
// fetch context pointer, and initiate xfer on all GPCs
|
|
ctx_xfer_exec:
|
|
ld b32 $r1 D[$r0 + #ctx_current]
|
|
mov $r2 0x414
|
|
shl b32 $r2 6
|
|
iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
|
|
mov $r14 -0x5b00
|
|
sethi $r14 0x410000
|
|
mov b32 $r15 $r1
|
|
call #nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
|
|
add b32 $r14 4
|
|
xbit $r15 $flags $p1
|
|
xbit $r2 $flags $p2
|
|
shl b32 $r2 1
|
|
or $r15 $r2
|
|
call #nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
|
|
|
|
// strands
|
|
mov $r1 0x4afc
|
|
sethi $r1 0x20000
|
|
mov $r2 0xc
|
|
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
|
|
call #strand_wait
|
|
mov $r2 0x47fc
|
|
sethi $r2 0x20000
|
|
iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
|
|
xbit $r2 $flags $p1
|
|
add b32 $r2 3
|
|
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
|
|
|
|
// mmio context
|
|
xbit $r10 $flags $p1 // direction
|
|
or $r10 6 // first, last
|
|
mov $r11 0 // base = 0
|
|
ld b32 $r12 D[$r0 + #hub_mmio_list_head]
|
|
ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
|
|
mov $r14 0 // not multi
|
|
call #mmctx_xfer
|
|
|
|
// wait for GPCs to all complete
|
|
mov $r10 8 // DONE_BAR
|
|
call #wait_doneo
|
|
|
|
// wait for strand xfer to complete
|
|
call #strand_wait
|
|
|
|
// post-op
|
|
bra $p1 #ctx_xfer_post
|
|
mov $r10 12 // DONE_UNK12
|
|
call #wait_donez
|
|
mov $r1 0xa10
|
|
shl b32 $r1 6
|
|
mov $r2 5
|
|
iowr I[$r1] $r2 // MEM_CMD
|
|
ctx_xfer_post_save_wait:
|
|
iord $r2 I[$r1]
|
|
or $r2 $r2
|
|
bra ne #ctx_xfer_post_save_wait
|
|
|
|
bra $p2 #ctx_xfer_done
|
|
ctx_xfer_post:
|
|
mov $r15 2
|
|
call #ctx_4170s
|
|
clear b32 $r15
|
|
call #ctx_86c
|
|
call #strand_post
|
|
call #ctx_4170w
|
|
clear b32 $r15
|
|
call #ctx_4170s
|
|
|
|
bra not $p1 #ctx_xfer_no_post_mmio
|
|
ld b32 $r1 D[$r0 + #chan_mmio_count]
|
|
or $r1 $r1
|
|
bra e #ctx_xfer_no_post_mmio
|
|
call #ctx_mmio_exec
|
|
|
|
ctx_xfer_no_post_mmio:
|
|
call #ctx_4160c
|
|
|
|
ctx_xfer_done:
|
|
ret
|
|
|
|
.align 256
|