361 lines
9.9 KiB
C
361 lines
9.9 KiB
C
#ifndef _IOCTL_H_
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#define _IOCTL_H_
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typedef struct rdmbuffer
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{
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ULONG Register;
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ULONG Length;
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}__attribute__((packed)) RDM_BUFFER, *PRDM_BUFFER;
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typedef struct wrmbuffer
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{
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ULONG Register;
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ULONG Length;
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UCHAR Data[4];
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}__attribute__((packed)) WRM_BUFFER, *PWRM_BUFFER;
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typedef struct ioctlbuffer
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{
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PVOID InputBuffer;
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ULONG InputLength;
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PVOID OutputBuffer;
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ULONG OutputLength;
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}__attribute__((packed)) IOCTL_BUFFER, *PIOCTL_BUFFER;
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typedef struct stGPIOInfo
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{
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UINT uiGpioNumber ; /* valid numbers 0-15 */
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UINT uiGpioValue; /* 1 set ; 0 not set */
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}__attribute__((packed))GPIO_INFO,*PGPIO_INFO;
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typedef struct stUserThreadReq
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{
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//0->Inactivate LED thread.
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//1->Activate the LED thread
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UINT ThreadState;
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}__attribute__((packed))USER_THREAD_REQ,*PUSER_THREAD_REQ;
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#define LED_THREAD_ACTIVATION_REQ 1
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////********** ioctl codes ***********////
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#define BCM_IOCTL 'k'
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//1.Control code for CONTROL MESSAGES
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#define IOCTL_SEND_CONTROL_MESSAGE _IOW(BCM_IOCTL, 0x801,int)
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//2.Control code to write a particular value to a particular register
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#define IOCTL_BCM_REGISTER_WRITE _IOW(BCM_IOCTL, 0x802, int) //
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//3.
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#define IOCTL_BCM_REGISTER_READ _IOR(BCM_IOCTL, 0x803, int) //
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//4.Control code to write x number of bytes to common memory
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//starting from address y
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#define IOCTL_BCM_COMMON_MEMORY_WRITE _IOW(BCM_IOCTL, 0x804, int)//
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//5.Control code to write x number of bytes to common memory
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//starting from address y
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#define IOCTL_BCM_COMMON_MEMORY_READ _IOR(BCM_IOCTL, 0x805, int)//
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//6.Control code for CONTROL MESSAGES
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#define IOCTL_GET_CONTROL_MESSAGE _IOR(BCM_IOCTL, 0x806, int)//
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//7.Control code for FIRMWARE DOWNLOAD
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#define IOCTL_BCM_FIRMWARE_DOWNLOAD _IOW(BCM_IOCTL, 0x807, int)//
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#define IOCTL_BCM_SET_SEND_VCID _IOW(BCM_IOCTL, 0x808, int)
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//9.Control code for TRANSFER MODE SWITCHING
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#define IOCTL_BCM_SWITCH_TRANSFER_MODE _IOW(BCM_IOCTL, 0x809, int)
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//10.Control code for LINK UP
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#define IOCTL_LINK_REQ _IOW(BCM_IOCTL, 0x80A, int)
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//11.Control code for RSSI Level Request
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#define IOCTL_RSSI_LEVEL_REQ _IOW(BCM_IOCTL, 0x80B, int)
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//12.Control code for IDLE MODE CONTROL
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#define IOCTL_IDLE_REQ _IOW(BCM_IOCTL, 0x80C, int)
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//13.Control code for SS/BS info
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#define IOCTL_SS_INFO_REQ _IOW(BCM_IOCTL, 0x80D, int)
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#define IOCTL_GET_STATISTICS_POINTER _IOW(BCM_IOCTL, 0x80E, int)
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#define IOCTL_CM_REQUEST _IOW(BCM_IOCTL, 0x80F, int)
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#define IOCTL_INIT_PARAM_REQ _IOW(BCM_IOCTL, 0x810, int)
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#define IOCTL_MAC_ADDR_REQ _IOW(BCM_IOCTL, 0x811, int)
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#define IOCTL_MAC_ADDR_RESP _IOWR(BCM_IOCTL, 0x812, int)
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#define IOCTL_CLASSIFICATION_RULE _IOW(BCM_IOCTL, 0x813, char)
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#define IOCTL_CLOSE_NOTIFICATION _IO(BCM_IOCTL, 0x814)
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#define IOCTL_LINK_UP _IO(BCM_IOCTL, 0x815)
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#define IOCTL_LINK_DOWN _IO(BCM_IOCTL, 0x816, IOCTL_BUFFER)
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#define IOCTL_CHIP_RESET _IO(BCM_IOCTL, 0x816)
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#define IOCTL_CINR_LEVEL_REQ _IOW(BCM_IOCTL, 0x817, char)
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#define IOCTL_WTM_CONTROL_REQ _IOW(BCM_IOCTL, 0x817,char)
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#define IOCTL_BE_BUCKET_SIZE _IOW(BCM_IOCTL, 0x818, unsigned long)
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#define IOCTL_RTPS_BUCKET_SIZE _IOW(BCM_IOCTL, 0x819, unsigned long)
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#define IOCTL_QOS_THRESHOLD _IOW(BCM_IOCTL, 0x820, unsigned long)
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#define IOCTL_DUMP_PACKET_INFO _IO(BCM_IOCTL, 0x821)
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#define IOCTL_GET_PACK_INFO _IOR(BCM_IOCTL, 0x823, int)
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#define IOCTL_BCM_GET_DRIVER_VERSION _IOR(BCM_IOCTL, 0x829, int)
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#define IOCTL_BCM_GET_CURRENT_STATUS _IOW(BCM_IOCTL, 0x828, int)
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#define IOCTL_BCM_GPIO_SET_REQUEST _IOW(BCM_IOCTL, 0x82A, int)
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#define IOCTL_BCM_GPIO_STATUS_REQUEST _IOW(BCM_IOCTL, 0x82b, int)
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#define IOCTL_BCM_GET_DSX_INDICATION _IOR(BCM_IOCTL, 0x854, int)
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#define IOCTL_BCM_BUFFER_DOWNLOAD_START _IOW(BCM_IOCTL, 0x855, int)
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#define IOCTL_BCM_BUFFER_DOWNLOAD _IOW(BCM_IOCTL, 0x856, int)
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#define IOCTL_BCM_BUFFER_DOWNLOAD_STOP _IOW(BCM_IOCTL, 0x857, int)
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#define IOCTL_BCM_REGISTER_WRITE_PRIVATE _IOW(BCM_IOCTL, 0x826, char)
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#define IOCTL_BCM_REGISTER_READ_PRIVATE _IOW(BCM_IOCTL, 0x827, char)
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#define IOCTL_BCM_SET_DEBUG _IOW(BCM_IOCTL, 0x824, IOCTL_BUFFER)
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#define IOCTL_BCM_EEPROM_REGISTER_WRITE _IOW(BCM_IOCTL, 0x858, int)
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#define IOCTL_BCM_EEPROM_REGISTER_READ _IOR(BCM_IOCTL, 0x859, int)
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#define IOCTL_BCM_WAKE_UP_DEVICE_FROM_IDLE _IOR(BCM_IOCTL, 0x860, int)
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#define IOCTL_BCM_SET_MAC_TRACING _IOW(BCM_IOCTL, 0x82c, int)
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#define IOCTL_BCM_GET_HOST_MIBS _IOW(BCM_IOCTL, 0x853, int)
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#define IOCTL_BCM_NVM_READ _IOR(BCM_IOCTL, 0x861, int)
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#define IOCTL_BCM_NVM_WRITE _IOW(BCM_IOCTL, 0x862, int)
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#define IOCTL_BCM_GET_NVM_SIZE _IOR(BCM_IOCTL, 0x863, int)
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#define IOCTL_BCM_CAL_INIT _IOR(BCM_IOCTL, 0x864, int)
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#define IOCTL_BCM_BULK_WRM _IOW(BCM_IOCTL, 0x90B, int)
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#define IOCTL_BCM_FLASH2X_SECTION_READ _IOR(BCM_IOCTL, 0x865, int)
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#define IOCTL_BCM_FLASH2X_SECTION_WRITE _IOW(BCM_IOCTL, 0x866, int)
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#define IOCTL_BCM_GET_FLASH2X_SECTION_BITMAP _IOR(BCM_IOCTL,0x867, int)
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#define IOCTL_BCM_SET_ACTIVE_SECTION _IOW(BCM_IOCTL,0x868, int)
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#define IOCTL_BCM_IDENTIFY_ACTIVE_SECTION _IO(BCM_IOCTL,0x869)
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#define IOCTL_BCM_COPY_SECTION _IOW(BCM_IOCTL, 0x870,int)
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#define IOCTL_BCM_GET_FLASH_CS_INFO _IOR(BCM_IOCTL, 0x871, int)
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#define IOCTL_BCM_SELECT_DSD _IOW(BCM_IOCTL, 0x872, int)
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#define IOCTL_BCM_NVM_RAW_READ _IOR(BCM_IOCTL, 0x875, int)
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#define IOCTL_BCM_CNTRLMSG_MASK _IOW(BCM_IOCTL, 0x874, int)
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#define IOCTL_BCM_GET_DEVICE_DRIVER_INFO _IOR(BCM_IOCTL, 0x877, int)
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#define IOCTL_BCM_TIME_SINCE_NET_ENTRY _IOR(BCM_IOCTL, 0x876, int)
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#define BCM_LED_THREAD_STATE_CHANGE_REQ _IOW(BCM_IOCTL, 0x878, int)
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#define IOCTL_BCM_GPIO_MULTI_REQUEST _IOW(BCM_IOCTL, 0x82D, IOCTL_BUFFER)
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#define IOCTL_BCM_GPIO_MODE_REQUEST _IOW(BCM_IOCTL, 0x82E, IOCTL_BUFFER)
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typedef enum _BCM_INTERFACE_TYPE
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{
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BCM_MII,
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BCM_CARDBUS,
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BCM_USB,
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BCM_SDIO,
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BCM_PCMCIA
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}BCM_INTERFACE_TYPE;
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typedef struct _DEVICE_DRIVER_INFO
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{
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NVM_TYPE u32NVMType;
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UINT MaxRDMBufferSize;
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BCM_INTERFACE_TYPE u32InterfaceType;
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UINT u32DSDStartOffset;
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UINT u32RxAlignmentCorrection;
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UINT u32Reserved[10];
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} DEVICE_DRIVER_INFO;
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typedef struct _NVM_READWRITE
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{
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void *pBuffer;
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// Data to be written from|read to. Memory should be allocated by the caller.
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uint32_t uiOffset;
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// offset at which data should be written to or read from.
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uint32_t uiNumBytes;
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// No. of bytes to be written or read.
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bool bVerify;
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// Applicable only for write. If set verification of written data will be done.
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} NVM_READWRITE,*PNVM_READWRITE;
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typedef struct bulkwrmbuffer
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{
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ULONG Register;
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ULONG SwapEndian;
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ULONG Values[1];
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}BULKWRM_BUFFER,*PBULKWRM_BUFFER;
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/***********Structure used for FlashMap2.x *******************************/
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/*
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* These are Sction present inside the Flash.
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* There is sectional RD/WR for flash Map 2.x.
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* hence these section will be used in read/write API.
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*/
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typedef enum _FLASH2X_SECTION_VAL
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{
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NO_SECTION_VAL = 0, //no section is choosen when absolute offset is given for RD/WR
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ISO_IMAGE1,
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ISO_IMAGE2,
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DSD0,
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DSD1,
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DSD2,
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VSA0,
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VSA1,
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VSA2,
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SCSI,
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CONTROL_SECTION,
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ISO_IMAGE1_PART2,
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ISO_IMAGE1_PART3,
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ISO_IMAGE2_PART2,
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ISO_IMAGE2_PART3,
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TOTAL_SECTIONS
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}FLASH2X_SECTION_VAL;
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/*
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* Structure used for READ/WRITE Flash Map2.x
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*/
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typedef struct _FLASH2X_READWRITE
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{
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FLASH2X_SECTION_VAL Section; //which section has to be read/written
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B_UINT32 offset; //Offset within Section.
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B_UINT32 numOfBytes; //NOB from the offset
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B_UINT32 bVerify;
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PVOID pDataBuff; //Buffer for reading/writing
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}FLASH2X_READWRITE, *PFLASH2X_READWRITE;
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/*
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* This structure is used for coping one section to other.
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* there are two ways to copy one section to other.
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* it NOB =0, complete section will be copied on to other.
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* if NOB !=0, only NOB will be copied from the given offset.
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*/
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typedef struct _FLASH2X_COPY_SECTION
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{
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//Src Section from which Data has to be copied to DstSection
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FLASH2X_SECTION_VAL SrcSection;
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//Destination Section from where Data has to be coppied.
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FLASH2X_SECTION_VAL DstSection;
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//Offset within Section. if NOB =0 it will be ignored and data will be coped from offset 0.
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B_UINT32 offset;
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//NOB from the offset. if NOB = 0 complete src section will be copied to Destination section.
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B_UINT32 numOfBytes;
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} FLASH2X_COPY_SECTION, *PFLASH2X_COPY_SECTION;
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typedef enum _SECTION_TYPE
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{
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ISO = 0,
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VSA = 1,
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DSD = 2
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} SECTION_TYPE, *PSECTION_TYPE;
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/*
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* This section provide the complete bitmap of the Flash.
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* using this map lib/APP will isssue read/write command.
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Fields are defined as :
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Bit [0] = section is present //1:present, 0: Not present
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* Bit [1] = section is valid //1: valid, 0: not valid
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* Bit [2] = Section is R/W //0: RW, 1: RO
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* Bit [3] = Section is Active or not 1 means Active, 0->inactive
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* Bit [7...3] = Reserved
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*/
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typedef struct _FLASH2X_BITMAP
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{
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UCHAR ISO_IMAGE1;
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UCHAR ISO_IMAGE2;
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UCHAR DSD0;
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UCHAR DSD1;
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UCHAR DSD2;
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UCHAR VSA0;
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UCHAR VSA1;
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UCHAR VSA2;
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UCHAR SCSI;
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UCHAR CONTROL_SECTION;
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//Reserved for future use
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UCHAR Reserved0;
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UCHAR Reserved1;
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UCHAR Reserved2;
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}FLASH2X_BITMAP, *PFLASH2X_BITMAP;
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//for net entry time check
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typedef struct _ST_TIME_ELAPSED_
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{
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ULONG64 ul64TimeElapsedSinceNetEntry;
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UINT32 uiReserved[4]; //By chance if required for future proofing
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}ST_TIME_ELAPSED,*PST_TIME_ELAPSED;
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enum {
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WIMAX_IDX=0, /*To access WiMAX chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE*/
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HOST_IDX, /*To access Host chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE*/
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MAX_IDX
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};
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typedef struct stGPIOMultiInfo
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{
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UINT uiGPIOCommand; /* 1 for set and 0 for get*/
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UINT uiGPIOMask; /* set the correspondig bit to 1 to access GPIO*/
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UINT uiGPIOValue; /* 0 or 1; value to be set when command is 1.*/
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}__attribute__((packed))GPIO_MULTI_INFO , *PGPIO_MULTI_INFO;
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typedef struct stGPIOMultiMode
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{
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UINT uiGPIOMode; /* 1 for OUT mode, 0 for IN mode*/
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UINT uiGPIOMask; /* GPIO mask to set mode*/
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}__attribute__((packed))GPIO_MULTI_MODE, *PGPIO_MULTI_MODE;
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#endif
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