9d99df4b10
On newer architectures (ARMv6, ARMv7), the depth of the prefetch and branch prediction is implementation defined and there is a small risk of wrong ASID tagging when changing TTBR0 before setting the new context id. The recommended solution is to set a reserved ASID during TTBR changing. This patch reserves ASID 0. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
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* linux/arch/arm/mm/context.c
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*
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* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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unsigned int cpu_last_asid = { 1 << ASID_BITS };
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/*
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* We fork()ed a process, and we need a new context for the child
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* to run in. We reserve version 0 for initial tasks so we will
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* always allocate an ASID. The ASID 0 is reserved for the TTBR
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* register changing sequence.
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*/
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.id = 0;
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}
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void __new_context(struct mm_struct *mm)
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{
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unsigned int asid;
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asid = ++cpu_last_asid;
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if (asid == 0)
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asid = cpu_last_asid = 1 << ASID_BITS;
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/*
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* If we've used up all our ASIDs, we need
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* to start a new version and flush the TLB.
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*/
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if ((asid & ~ASID_MASK) == 0) {
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asid = ++cpu_last_asid;
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/* set the reserved ASID before flushing the TLB */
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asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n"
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:
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: "r" (0));
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isb();
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flush_tlb_all();
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}
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mm->context.id = asid;
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}
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