b8b572e101
from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
87 lines
4.2 KiB
C
87 lines
4.2 KiB
C
#ifndef _ASM_POWERPC_SIGCONTEXT_H
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#define _ASM_POWERPC_SIGCONTEXT_H
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/compiler.h>
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#include <asm/ptrace.h>
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#ifdef __powerpc64__
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#include <asm/elf.h>
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#endif
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struct sigcontext {
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unsigned long _unused[4];
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int signal;
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#ifdef __powerpc64__
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int _pad0;
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#endif
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unsigned long handler;
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unsigned long oldmask;
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struct pt_regs __user *regs;
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#ifdef __powerpc64__
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elf_gregset_t gp_regs;
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elf_fpregset_t fp_regs;
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/*
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* To maintain compatibility with current implementations the sigcontext is
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* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
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* followed by an unstructured (vmx_reserve) field of 69 doublewords. This
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* allows the array of vector registers to be quadword aligned independent of
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* the alignment of the containing sigcontext or ucontext. It is the
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* responsibility of the code setting the sigcontext to set this pointer to
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* either NULL (if this processor does not support the VMX feature) or the
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* address of the first quadword within the allocated (vmx_reserve) area.
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*
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* The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
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* an array of 34 quadword entries (elf_vrregset_t). The entries with
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* indexes 0-31 contain the corresponding vector registers. The entry with
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* index 32 contains the vscr as the last word (offset 12) within the
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* quadword. This allows the vscr to be stored as either a quadword (since
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* it must be copied via a vector register to/from storage) or as a word.
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* The entry with index 33 contains the vrsave as the first word (offset 0)
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* within the quadword.
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*
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* Part of the VSX data is stored here also by extending vmx_restore
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* by an additional 32 double words. Architecturally the layout of
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* the VSR registers and how they overlap on top of the legacy FPR and
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* VR registers is shown below:
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*
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* VSR doubleword 0 VSR doubleword 1
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* ----------------------------------------------------------------
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* VSR[0] | FPR[0] | |
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* ----------------------------------------------------------------
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* VSR[1] | FPR[1] | |
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* ----------------------------------------------------------------
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* | ... | |
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* | ... | |
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* ----------------------------------------------------------------
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* VSR[30] | FPR[30] | |
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* ----------------------------------------------------------------
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* VSR[31] | FPR[31] | |
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* ----------------------------------------------------------------
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* VSR[32] | VR[0] |
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* ----------------------------------------------------------------
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* VSR[33] | VR[1] |
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* ----------------------------------------------------------------
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* | ... |
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* | ... |
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* ----------------------------------------------------------------
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* VSR[62] | VR[30] |
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* ----------------------------------------------------------------
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* VSR[63] | VR[31] |
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* ----------------------------------------------------------------
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*
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* FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
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* is stored at the start of vmx_reserve. vmx_reserve is extended for
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* backwards compatility to store VSR 0-31 doubleword 1 after the VMX
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* registers and vscr/vrsave.
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*/
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elf_vrreg_t __user *v_regs;
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long vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
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#endif
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};
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#endif /* _ASM_POWERPC_SIGCONTEXT_H */
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