38faddb1af
The behavior of Nvidia HDMI codec regarding the pin-detection unsol events is based on the old HD-audio spec, i.e. PD bit indicates only the update and doesn't show the current state. Since the current code assumes the new behavior, the pin-detection doesn't work relialby with these h/w. This patch adds a flag for indicating the old spec, and fixes the issue by checking the pin-detection explicitly for such hardware. Tested-by: Wei Ni <wni@nvidia.com> Cc: <stable@kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
598 lines
16 KiB
C
598 lines
16 KiB
C
/*
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* Universal Interface for Intel High Definition Audio Codec
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*
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* HD audio interface patch for NVIDIA HDMI codecs
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*
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* Copyright (c) 2008 NVIDIA Corp. All rights reserved.
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* Copyright (c) 2008 Wei Ni <wni@nvidia.com>
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*
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*
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* This driver is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include "hda_codec.h"
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#include "hda_local.h"
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#define MAX_HDMI_CVTS 1
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#define MAX_HDMI_PINS 1
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#include "patch_hdmi.c"
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static char *nvhdmi_pcm_names[MAX_HDMI_CVTS] = {
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"NVIDIA HDMI",
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};
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/* define below to restrict the supported rates and formats */
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/* #define LIMITED_RATE_FMT_SUPPORT */
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enum HDACodec {
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HDA_CODEC_NVIDIA_MCP7X,
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HDA_CODEC_NVIDIA_MCP89,
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HDA_CODEC_NVIDIA_GT21X,
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HDA_CODEC_INVALID
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};
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#define Nv_VERB_SET_Channel_Allocation 0xF79
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#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
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#define Nv_VERB_SET_Audio_Protection_On 0xF98
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#define Nv_VERB_SET_Audio_Protection_Off 0xF99
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#define nvhdmi_master_con_nid_7x 0x04
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#define nvhdmi_master_pin_nid_7x 0x05
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#define nvhdmi_master_con_nid_89 0x04
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#define nvhdmi_master_pin_nid_89 0x05
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static hda_nid_t nvhdmi_con_nids_7x[4] = {
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/*front, rear, clfe, rear_surr */
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0x6, 0x8, 0xa, 0xc,
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};
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static struct hda_verb nvhdmi_basic_init_7x[] = {
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/* set audio protect on */
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{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
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/* enable digital output on pin widget */
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{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
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{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
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{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
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{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
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{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
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{} /* terminator */
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};
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#ifdef LIMITED_RATE_FMT_SUPPORT
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/* support only the safe format and rate */
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#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
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#define SUPPORTED_MAXBPS 16
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#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
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#else
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/* support all rates and formats */
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#define SUPPORTED_RATES \
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(SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
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SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
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SNDRV_PCM_RATE_192000)
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#define SUPPORTED_MAXBPS 24
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#define SUPPORTED_FORMATS \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
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#endif
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/*
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* Controls
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*/
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static int nvhdmi_build_controls(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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int err;
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int i;
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if ((spec->codec_type == HDA_CODEC_NVIDIA_MCP89)
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|| (spec->codec_type == HDA_CODEC_NVIDIA_GT21X)) {
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for (i = 0; i < codec->num_pcms; i++) {
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err = snd_hda_create_spdif_out_ctls(codec,
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spec->cvt[i]);
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if (err < 0)
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return err;
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}
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} else {
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err = snd_hda_create_spdif_out_ctls(codec,
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spec->multiout.dig_out_nid);
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if (err < 0)
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return err;
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}
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return 0;
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}
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static int nvhdmi_init(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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int i;
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if ((spec->codec_type == HDA_CODEC_NVIDIA_MCP89)
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|| (spec->codec_type == HDA_CODEC_NVIDIA_GT21X)) {
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for (i = 0; spec->pin[i]; i++) {
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hdmi_enable_output(codec, spec->pin[i]);
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snd_hda_codec_write(codec, spec->pin[i], 0,
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AC_VERB_SET_UNSOLICITED_ENABLE,
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AC_USRSP_EN | spec->pin[i]);
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}
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} else {
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snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
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}
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return 0;
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}
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static void nvhdmi_free(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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int i;
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if ((spec->codec_type == HDA_CODEC_NVIDIA_MCP89)
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|| (spec->codec_type == HDA_CODEC_NVIDIA_GT21X)) {
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for (i = 0; i < spec->num_pins; i++)
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snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
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}
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kfree(spec);
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}
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/*
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* Digital out
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*/
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static int nvhdmi_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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struct snd_pcm_substream *substream)
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{
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struct hdmi_spec *spec = codec->spec;
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return snd_hda_multi_out_dig_open(codec, &spec->multiout);
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}
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static int nvhdmi_dig_playback_pcm_close_8ch_7x(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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struct snd_pcm_substream *substream)
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{
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struct hdmi_spec *spec = codec->spec;
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int i;
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snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
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0, AC_VERB_SET_CHANNEL_STREAMID, 0);
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for (i = 0; i < 4; i++) {
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/* set the stream id */
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snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
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AC_VERB_SET_CHANNEL_STREAMID, 0);
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/* set the stream format */
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snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
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AC_VERB_SET_STREAM_FORMAT, 0);
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}
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return snd_hda_multi_out_dig_close(codec, &spec->multiout);
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}
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static int nvhdmi_dig_playback_pcm_close_2ch(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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struct snd_pcm_substream *substream)
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{
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struct hdmi_spec *spec = codec->spec;
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return snd_hda_multi_out_dig_close(codec, &spec->multiout);
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}
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static int nvhdmi_dig_playback_pcm_prepare_8ch_89(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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unsigned int stream_tag,
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unsigned int format,
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struct snd_pcm_substream *substream)
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{
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hdmi_set_channel_count(codec, hinfo->nid,
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substream->runtime->channels);
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hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
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hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
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return 0;
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}
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static int nvhdmi_dig_playback_pcm_prepare_8ch(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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unsigned int stream_tag,
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unsigned int format,
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struct snd_pcm_substream *substream)
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{
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int chs;
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unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
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int i;
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mutex_lock(&codec->spdif_mutex);
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chs = substream->runtime->channels;
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chan = chs ? (chs - 1) : 1;
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switch (chs) {
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default:
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case 0:
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case 2:
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chanmask = 0x00;
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break;
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case 4:
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chanmask = 0x08;
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break;
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case 6:
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chanmask = 0x0b;
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break;
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case 8:
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chanmask = 0x13;
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break;
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}
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dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
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dataDCC2 = 0x2;
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/* set the Audio InforFrame Channel Allocation */
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snd_hda_codec_write(codec, 0x1, 0,
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Nv_VERB_SET_Channel_Allocation, chanmask);
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/* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
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if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
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snd_hda_codec_write(codec,
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nvhdmi_master_con_nid_7x,
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0,
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AC_VERB_SET_DIGI_CONVERT_1,
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codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
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/* set the stream id */
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snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
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AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
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/* set the stream format */
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snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
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AC_VERB_SET_STREAM_FORMAT, format);
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/* turn on again (if needed) */
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/* enable and set the channel status audio/data flag */
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if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
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snd_hda_codec_write(codec,
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nvhdmi_master_con_nid_7x,
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0,
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AC_VERB_SET_DIGI_CONVERT_1,
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codec->spdif_ctls & 0xff);
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snd_hda_codec_write(codec,
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nvhdmi_master_con_nid_7x,
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0,
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AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
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}
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for (i = 0; i < 4; i++) {
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if (chs == 2)
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channel_id = 0;
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else
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channel_id = i * 2;
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/* turn off SPDIF once;
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*otherwise the IEC958 bits won't be updated
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*/
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if (codec->spdif_status_reset &&
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(codec->spdif_ctls & AC_DIG1_ENABLE))
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snd_hda_codec_write(codec,
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nvhdmi_con_nids_7x[i],
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0,
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AC_VERB_SET_DIGI_CONVERT_1,
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codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
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/* set the stream id */
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snd_hda_codec_write(codec,
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nvhdmi_con_nids_7x[i],
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0,
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AC_VERB_SET_CHANNEL_STREAMID,
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(stream_tag << 4) | channel_id);
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/* set the stream format */
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snd_hda_codec_write(codec,
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nvhdmi_con_nids_7x[i],
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0,
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AC_VERB_SET_STREAM_FORMAT,
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format);
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/* turn on again (if needed) */
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/* enable and set the channel status audio/data flag */
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if (codec->spdif_status_reset &&
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(codec->spdif_ctls & AC_DIG1_ENABLE)) {
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snd_hda_codec_write(codec,
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nvhdmi_con_nids_7x[i],
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0,
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AC_VERB_SET_DIGI_CONVERT_1,
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codec->spdif_ctls & 0xff);
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snd_hda_codec_write(codec,
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nvhdmi_con_nids_7x[i],
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0,
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AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
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}
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}
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/* set the Audio Info Frame Checksum */
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snd_hda_codec_write(codec, 0x1, 0,
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Nv_VERB_SET_Info_Frame_Checksum,
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(0x71 - chan - chanmask));
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mutex_unlock(&codec->spdif_mutex);
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return 0;
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}
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static int nvhdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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struct snd_pcm_substream *substream)
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{
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return 0;
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}
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static int nvhdmi_dig_playback_pcm_prepare_2ch(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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unsigned int stream_tag,
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unsigned int format,
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struct snd_pcm_substream *substream)
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{
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struct hdmi_spec *spec = codec->spec;
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return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag,
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format, substream);
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}
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static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch_89 = {
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.substreams = 1,
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.channels_min = 2,
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.rates = SUPPORTED_RATES,
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.maxbps = SUPPORTED_MAXBPS,
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.formats = SUPPORTED_FORMATS,
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.ops = {
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.prepare = nvhdmi_dig_playback_pcm_prepare_8ch_89,
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.cleanup = nvhdmi_playback_pcm_cleanup,
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},
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};
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static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch_7x = {
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.substreams = 1,
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.channels_min = 2,
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.channels_max = 8,
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.nid = nvhdmi_master_con_nid_7x,
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.rates = SUPPORTED_RATES,
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.maxbps = SUPPORTED_MAXBPS,
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.formats = SUPPORTED_FORMATS,
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.ops = {
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.open = nvhdmi_dig_playback_pcm_open,
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.close = nvhdmi_dig_playback_pcm_close_8ch_7x,
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.prepare = nvhdmi_dig_playback_pcm_prepare_8ch
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},
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};
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static struct hda_pcm_stream nvhdmi_pcm_digital_playback_2ch = {
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.substreams = 1,
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.channels_min = 2,
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.channels_max = 2,
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.nid = nvhdmi_master_con_nid_7x,
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.rates = SUPPORTED_RATES,
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.maxbps = SUPPORTED_MAXBPS,
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.formats = SUPPORTED_FORMATS,
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.ops = {
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.open = nvhdmi_dig_playback_pcm_open,
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.close = nvhdmi_dig_playback_pcm_close_2ch,
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.prepare = nvhdmi_dig_playback_pcm_prepare_2ch
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},
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};
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static int nvhdmi_build_pcms_8ch_89(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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struct hda_pcm *info = spec->pcm_rec;
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int i;
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codec->num_pcms = spec->num_cvts;
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codec->pcm_info = info;
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for (i = 0; i < codec->num_pcms; i++, info++) {
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unsigned int chans;
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chans = get_wcaps(codec, spec->cvt[i]);
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chans = get_wcaps_channels(chans);
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info->name = nvhdmi_pcm_names[i];
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info->pcm_type = HDA_PCM_TYPE_HDMI;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK]
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= nvhdmi_pcm_digital_playback_8ch_89;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->cvt[i];
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info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = chans;
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}
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return 0;
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}
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static int nvhdmi_build_pcms_8ch_7x(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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struct hda_pcm *info = spec->pcm_rec;
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codec->num_pcms = 1;
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codec->pcm_info = info;
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info->name = "NVIDIA HDMI";
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info->pcm_type = HDA_PCM_TYPE_HDMI;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK]
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= nvhdmi_pcm_digital_playback_8ch_7x;
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return 0;
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}
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static int nvhdmi_build_pcms_2ch(struct hda_codec *codec)
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{
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struct hdmi_spec *spec = codec->spec;
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struct hda_pcm *info = spec->pcm_rec;
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codec->num_pcms = 1;
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codec->pcm_info = info;
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info->name = "NVIDIA HDMI";
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info->pcm_type = HDA_PCM_TYPE_HDMI;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK]
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= nvhdmi_pcm_digital_playback_2ch;
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return 0;
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}
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static struct hda_codec_ops nvhdmi_patch_ops_8ch_89 = {
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.build_controls = nvhdmi_build_controls,
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.build_pcms = nvhdmi_build_pcms_8ch_89,
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.init = nvhdmi_init,
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.free = nvhdmi_free,
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.unsol_event = hdmi_unsol_event,
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};
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static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
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.build_controls = nvhdmi_build_controls,
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.build_pcms = nvhdmi_build_pcms_8ch_7x,
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.init = nvhdmi_init,
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.free = nvhdmi_free,
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};
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static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
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.build_controls = nvhdmi_build_controls,
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.build_pcms = nvhdmi_build_pcms_2ch,
|
|
.init = nvhdmi_init,
|
|
.free = nvhdmi_free,
|
|
};
|
|
|
|
static int patch_nvhdmi_8ch_89(struct hda_codec *codec)
|
|
{
|
|
struct hdmi_spec *spec;
|
|
int i;
|
|
|
|
spec = kzalloc(sizeof(*spec), GFP_KERNEL);
|
|
if (spec == NULL)
|
|
return -ENOMEM;
|
|
|
|
codec->spec = spec;
|
|
spec->codec_type = HDA_CODEC_NVIDIA_MCP89;
|
|
spec->old_pin_detect = 1;
|
|
|
|
if (hdmi_parse_codec(codec) < 0) {
|
|
codec->spec = NULL;
|
|
kfree(spec);
|
|
return -EINVAL;
|
|
}
|
|
codec->patch_ops = nvhdmi_patch_ops_8ch_89;
|
|
|
|
for (i = 0; i < spec->num_pins; i++)
|
|
snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
|
|
|
|
init_channel_allocations();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
|
|
{
|
|
struct hdmi_spec *spec;
|
|
|
|
spec = kzalloc(sizeof(*spec), GFP_KERNEL);
|
|
if (spec == NULL)
|
|
return -ENOMEM;
|
|
|
|
codec->spec = spec;
|
|
|
|
spec->multiout.num_dacs = 0; /* no analog */
|
|
spec->multiout.max_channels = 8;
|
|
spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
|
|
spec->codec_type = HDA_CODEC_NVIDIA_MCP7X;
|
|
spec->old_pin_detect = 1;
|
|
|
|
codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int patch_nvhdmi_2ch(struct hda_codec *codec)
|
|
{
|
|
struct hdmi_spec *spec;
|
|
|
|
spec = kzalloc(sizeof(*spec), GFP_KERNEL);
|
|
if (spec == NULL)
|
|
return -ENOMEM;
|
|
|
|
codec->spec = spec;
|
|
|
|
spec->multiout.num_dacs = 0; /* no analog */
|
|
spec->multiout.max_channels = 2;
|
|
spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
|
|
spec->codec_type = HDA_CODEC_NVIDIA_MCP7X;
|
|
spec->old_pin_detect = 1;
|
|
|
|
codec->patch_ops = nvhdmi_patch_ops_2ch;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* patch entries
|
|
*/
|
|
static struct hda_codec_preset snd_hda_preset_nvhdmi[] = {
|
|
{ .id = 0x10de0002, .name = "MCP77/78 HDMI",
|
|
.patch = patch_nvhdmi_8ch_7x },
|
|
{ .id = 0x10de0003, .name = "MCP77/78 HDMI",
|
|
.patch = patch_nvhdmi_8ch_7x },
|
|
{ .id = 0x10de0005, .name = "MCP77/78 HDMI",
|
|
.patch = patch_nvhdmi_8ch_7x },
|
|
{ .id = 0x10de0006, .name = "MCP77/78 HDMI",
|
|
.patch = patch_nvhdmi_8ch_7x },
|
|
{ .id = 0x10de0007, .name = "MCP79/7A HDMI",
|
|
.patch = patch_nvhdmi_8ch_7x },
|
|
{ .id = 0x10de000a, .name = "GT220 HDMI",
|
|
.patch = patch_nvhdmi_8ch_89 },
|
|
{ .id = 0x10de000b, .name = "GT21x HDMI",
|
|
.patch = patch_nvhdmi_8ch_89 },
|
|
{ .id = 0x10de000c, .name = "MCP89 HDMI",
|
|
.patch = patch_nvhdmi_8ch_89 },
|
|
{ .id = 0x10de000d, .name = "GT240 HDMI",
|
|
.patch = patch_nvhdmi_8ch_89 },
|
|
{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
|
|
{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
|
|
{} /* terminator */
|
|
};
|
|
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0002");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0003");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0005");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0006");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0007");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de000a");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de000b");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de000c");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de000d");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de0067");
|
|
MODULE_ALIAS("snd-hda-codec-id:10de8001");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("NVIDIA HDMI HD-audio codec");
|
|
|
|
static struct hda_codec_preset_list nvhdmi_list = {
|
|
.preset = snd_hda_preset_nvhdmi,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int __init patch_nvhdmi_init(void)
|
|
{
|
|
return snd_hda_add_codec_preset(&nvhdmi_list);
|
|
}
|
|
|
|
static void __exit patch_nvhdmi_exit(void)
|
|
{
|
|
snd_hda_delete_codec_preset(&nvhdmi_list);
|
|
}
|
|
|
|
module_init(patch_nvhdmi_init)
|
|
module_exit(patch_nvhdmi_exit)
|