722202e10b
Recent SoC such as Armada 370/XP came with the possibility to deal with the I/O coherency by hardware. In this case the transaction attribute of the window must be flagged as "Shared transaction". Once this flag is set, then the transactions will be forced to be sent through the coherency block, in other case transaction is driven directly to DRAM. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Yehuda Yitschak <yehuday@marvell.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
175 lines
4 KiB
C
175 lines
4 KiB
C
/*
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* arch/arm/plat-orion/addr-map.c
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*
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* Address map functions for Marvell Orion based SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <plat/addr-map.h>
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struct mbus_dram_target_info orion_mbus_dram_info;
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const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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return &orion_mbus_dram_info;
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}
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EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
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/*
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* DDR target is the same on all Orion platforms.
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*/
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#define TARGET_DDR 0
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN_CTRL_OFF 0x0000
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#define WIN_BASE_OFF 0x0004
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_HI_OFF 0x000c
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#define ATTR_HW_COHERENCY (0x1 << 4)
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/*
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* Default implementation
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*/
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static void __init __iomem *
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orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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return cfg->bridge_virt_base + (win << 4);
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}
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/*
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* Default implementation
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*/
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static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
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const int win)
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{
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if (win < cfg->remappable_wins)
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return 1;
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return 0;
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}
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void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
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const int win, const u32 base,
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const u32 size, const u8 target,
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const u8 attr, const int remap)
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{
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void __iomem *addr = cfg->win_cfg_base(cfg, win);
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u32 ctrl, base_high, remap_addr;
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if (win >= cfg->num_wins) {
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printk(KERN_ERR "setup_cpu_win: trying to allocate window "
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"%d when only %d allowed\n", win, cfg->num_wins);
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}
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base_high = base & 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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writel(base_high, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (cfg->cpu_win_can_remap(cfg, win)) {
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if (remap < 0)
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remap_addr = base;
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else
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remap_addr = remap;
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writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/*
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* Configure a number of windows.
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*/
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static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
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const struct orion_addr_map_info *info)
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{
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while (info->win != -1) {
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orion_setup_cpu_win(cfg, info->win, info->base, info->size,
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info->target, info->attr, info->remap);
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info++;
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}
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}
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static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
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{
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void __iomem *addr;
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int i;
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for (i = 0; i < cfg->num_wins; i++) {
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addr = cfg->win_cfg_base(cfg, i);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (cfg->cpu_win_can_remap(cfg, i)) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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}
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/*
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* Disable, clear and configure windows.
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*/
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void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
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const struct orion_addr_map_info *info)
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{
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if (!cfg->cpu_win_can_remap)
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cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
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if (!cfg->win_cfg_base)
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cfg->win_cfg_base = orion_win_cfg_base;
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orion_disable_wins(cfg);
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if (info)
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orion_setup_cpu_wins(cfg, info);
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}
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/*
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* Setup MBUS dram target info.
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*/
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void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
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const void __iomem *ddr_window_cpu_base)
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{
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int i;
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int cs;
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orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &orion_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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if (cfg->hw_io_coherency)
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w->mbus_attr |= ATTR_HW_COHERENCY;
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w->base = base & 0xffff0000;
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w->size = (size | 0x0000ffff) + 1;
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}
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}
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orion_mbus_dram_info.num_cs = cs;
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}
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