9959c888a3
I have a system with lots of igb and ixgbe, when iov/vf are
enabled for them, we hit the limit of 3064.
when system has 20 pcie installed, and one card has 2
functions, and one function needs 64 msi-x,
may need 20 * 2 * 64 = 2560 for msi-x
but if iov and vf are enabled
may need 20 * 2 * 64 * 3 = 7680 for msi-x
assume system with 5 ioapic, nr_irqs_gsi will be 120.
NR_CPUS = 512, and nr_cpu_ids = 128
will have NR_IRQS = 256 + 512 * 64 = 33024
will have nr_irqs = 120 + 8 * 128 + 120 * 64 = 8824
When SPARSE_IRQ is not set, there is no increase with kernel data
size.
when NR_CPUS=128, and SPARSE_IRQ is set:
text data bss dec hex filename
21837444 4216564 12480736 38534744 24bfe58 vmlinux.before
21837442 4216580 12480736 38534758 24bfe66 vmlinux.after
when NR_CPUS=4096, and SPARSE_IRQ is set
text data bss dec hex filename
21878619 5610244 13415392 40904255 270263f vmlinux.before
21878617 5610244 13415392 40904253 270263d vmlinux.after
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <4B398ECD.1080506@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
#ifndef _ASM_X86_IRQ_VECTORS_H
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#define _ASM_X86_IRQ_VECTORS_H
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/*
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* Linux IRQ vector layout.
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*
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* There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
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* be defined by Linux. They are used as a jump table by the CPU when a
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* given vector is triggered - by a CPU-external, CPU-internal or
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* software-triggered event.
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*
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* Linux sets the kernel code address each entry jumps to early during
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* bootup, and never changes them. This is the general layout of the
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* IDT entries:
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*
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* Vectors 0 ... 31 : system traps and exceptions - hardcoded events
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* Vectors 32 ... 127 : device interrupts
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* Vector 128 : legacy int80 syscall interface
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* Vectors 129 ... 237 : device interrupts
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* Vectors 238 ... 255 : special interrupts
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*
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* 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
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*
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* This file enumerates the exact layout of them:
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*/
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#define NMI_VECTOR 0x02
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#define MCE_VECTOR 0x12
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/*
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* IDT vectors usable for external interrupt sources start
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* at 0x20:
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*/
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#define FIRST_EXTERNAL_VECTOR 0x20
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#ifdef CONFIG_X86_32
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# define SYSCALL_VECTOR 0x80
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# define IA32_SYSCALL_VECTOR 0x80
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#else
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# define IA32_SYSCALL_VECTOR 0x80
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#endif
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/*
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* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
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* cleanup after irq migration.
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*/
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#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
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/*
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* Vectors 0x30-0x3f are used for ISA interrupts.
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*/
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
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#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
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#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
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#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
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#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
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#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
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#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
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#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
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#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
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#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
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#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
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#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
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#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
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#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
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#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
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#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
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/*
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* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
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*
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* some of the following vectors are 'rare', they are merged
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* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
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* TLB, reschedule and local APIC vectors are performance-critical.
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*/
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#define SPURIOUS_APIC_VECTOR 0xff
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/*
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* Sanity check
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*/
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#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
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# error SPURIOUS_APIC_VECTOR definition error
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#endif
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#define ERROR_APIC_VECTOR 0xfe
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#define RESCHEDULE_VECTOR 0xfd
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#define CALL_FUNCTION_VECTOR 0xfc
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#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
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#define THERMAL_APIC_VECTOR 0xfa
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#define THRESHOLD_APIC_VECTOR 0xf9
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#define REBOOT_VECTOR 0xf8
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/* f0-f7 used for spreading out TLB flushes: */
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#define INVALIDATE_TLB_VECTOR_END 0xf7
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#define INVALIDATE_TLB_VECTOR_START 0xf0
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#define NUM_INVALIDATE_TLB_VECTORS 8
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/*
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* Local APIC timer IRQ vector is on a different priority level,
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* to work around the 'lost local interrupt if more than 2 IRQ
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* sources per level' errata.
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*/
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#define LOCAL_TIMER_VECTOR 0xef
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/*
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* Generic system vector for platform specific use
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*/
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#define X86_PLATFORM_IPI_VECTOR 0xed
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/*
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* Performance monitoring pending work vector:
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*/
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#define LOCAL_PENDING_VECTOR 0xec
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#define UV_BAU_MESSAGE 0xea
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/*
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* Self IPI vector for machine checks
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*/
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#define MCE_SELF_VECTOR 0xeb
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/*
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* First APIC vector available to drivers: (vectors 0x30-0xee) we
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* start at 0x31(0x41) to spread out vectors evenly between priority
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* levels. (0x80 is the syscall vector)
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*/
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#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
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#define NR_VECTORS 256
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#define FPU_IRQ 13
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#define FIRST_VM86_IRQ 3
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#define LAST_VM86_IRQ 15
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#ifndef __ASSEMBLY__
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static inline int invalid_vm86_irq(int irq)
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{
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return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ;
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}
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#endif
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/*
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* Size the maximum number of interrupts.
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*
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* If the irq_desc[] array has a sparse layout, we can size things
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* generously - it scales up linearly with the maximum number of CPUs,
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* and the maximum number of IO-APICs, whichever is higher.
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*
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* In other cases we size more conservatively, to not create too large
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* static arrays.
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*/
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#define NR_IRQS_LEGACY 16
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#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS )
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#ifdef CONFIG_X86_IO_APIC
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# ifdef CONFIG_SPARSE_IRQ
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# define CPU_VECTOR_LIMIT (64 * NR_CPUS)
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# define NR_IRQS \
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(CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
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(NR_VECTORS + CPU_VECTOR_LIMIT) : \
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(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
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# else
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# define CPU_VECTOR_LIMIT (32 * NR_CPUS)
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# define NR_IRQS \
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(CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \
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(NR_VECTORS + CPU_VECTOR_LIMIT) : \
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(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
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# endif
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#else /* !CONFIG_X86_IO_APIC: */
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# define NR_IRQS NR_IRQS_LEGACY
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#endif
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#endif /* _ASM_X86_IRQ_VECTORS_H */
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