b285192a43
Rename all PCI drivers with their own directory under drivers/media/video into drivers/media/pci and update the building system. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
220 lines
6 KiB
C
220 lines
6 KiB
C
/*
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* Zoran ZR36060 basic configuration functions - header file
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*
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* Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
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*
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* $Id: zr36060.h,v 1.1.1.1.2.3 2003/01/14 21:18:47 rbultje Exp $
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*
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* ------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* ------------------------------------------------------------------------
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*/
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#ifndef ZR36060_H
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#define ZR36060_H
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#include "videocodec.h"
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/* data stored for each zoran jpeg codec chip */
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struct zr36060 {
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char name[32];
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int num;
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/* io datastructure */
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struct videocodec *codec;
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// last coder status
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__u8 status;
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// actual coder setup
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int mode;
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__u16 width;
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__u16 height;
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__u16 bitrate_ctrl;
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__u32 total_code_vol;
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__u32 real_code_vol;
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__u16 max_block_vol;
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__u8 h_samp_ratio[8];
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__u8 v_samp_ratio[8];
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__u16 scalefact;
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__u16 dri;
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/* app/com marker data */
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struct jpeg_app_marker app;
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struct jpeg_com_marker com;
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};
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/* ZR36060 register addresses */
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#define ZR060_LOAD 0x000
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#define ZR060_CFSR 0x001
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#define ZR060_CIR 0x002
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#define ZR060_CMR 0x003
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#define ZR060_MBZ 0x004
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#define ZR060_MBCVR 0x005
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#define ZR060_MER 0x006
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#define ZR060_IMR 0x007
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#define ZR060_ISR 0x008
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#define ZR060_TCV_NET_HI 0x009
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#define ZR060_TCV_NET_MH 0x00a
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#define ZR060_TCV_NET_ML 0x00b
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#define ZR060_TCV_NET_LO 0x00c
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#define ZR060_TCV_DATA_HI 0x00d
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#define ZR060_TCV_DATA_MH 0x00e
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#define ZR060_TCV_DATA_ML 0x00f
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#define ZR060_TCV_DATA_LO 0x010
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#define ZR060_SF_HI 0x011
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#define ZR060_SF_LO 0x012
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#define ZR060_AF_HI 0x013
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#define ZR060_AF_M 0x014
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#define ZR060_AF_LO 0x015
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#define ZR060_ACV_HI 0x016
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#define ZR060_ACV_MH 0x017
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#define ZR060_ACV_ML 0x018
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#define ZR060_ACV_LO 0x019
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#define ZR060_ACT_HI 0x01a
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#define ZR060_ACT_MH 0x01b
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#define ZR060_ACT_ML 0x01c
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#define ZR060_ACT_LO 0x01d
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#define ZR060_ACV_TRUN_HI 0x01e
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#define ZR060_ACV_TRUN_MH 0x01f
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#define ZR060_ACV_TRUN_ML 0x020
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#define ZR060_ACV_TRUN_LO 0x021
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#define ZR060_IDR_DEV 0x022
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#define ZR060_IDR_REV 0x023
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#define ZR060_TCR_HI 0x024
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#define ZR060_TCR_LO 0x025
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#define ZR060_VCR 0x030
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#define ZR060_VPR 0x031
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#define ZR060_SR 0x032
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#define ZR060_BCR_Y 0x033
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#define ZR060_BCR_U 0x034
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#define ZR060_BCR_V 0x035
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#define ZR060_SGR_VTOTAL_HI 0x036
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#define ZR060_SGR_VTOTAL_LO 0x037
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#define ZR060_SGR_HTOTAL_HI 0x038
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#define ZR060_SGR_HTOTAL_LO 0x039
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#define ZR060_SGR_VSYNC 0x03a
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#define ZR060_SGR_HSYNC 0x03b
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#define ZR060_SGR_BVSTART 0x03c
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#define ZR060_SGR_BHSTART 0x03d
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#define ZR060_SGR_BVEND_HI 0x03e
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#define ZR060_SGR_BVEND_LO 0x03f
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#define ZR060_SGR_BHEND_HI 0x040
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#define ZR060_SGR_BHEND_LO 0x041
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#define ZR060_AAR_VSTART_HI 0x042
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#define ZR060_AAR_VSTART_LO 0x043
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#define ZR060_AAR_VEND_HI 0x044
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#define ZR060_AAR_VEND_LO 0x045
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#define ZR060_AAR_HSTART_HI 0x046
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#define ZR060_AAR_HSTART_LO 0x047
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#define ZR060_AAR_HEND_HI 0x048
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#define ZR060_AAR_HEND_LO 0x049
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#define ZR060_SWR_VSTART_HI 0x04a
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#define ZR060_SWR_VSTART_LO 0x04b
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#define ZR060_SWR_VEND_HI 0x04c
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#define ZR060_SWR_VEND_LO 0x04d
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#define ZR060_SWR_HSTART_HI 0x04e
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#define ZR060_SWR_HSTART_LO 0x04f
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#define ZR060_SWR_HEND_HI 0x050
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#define ZR060_SWR_HEND_LO 0x051
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#define ZR060_SOF_IDX 0x060
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#define ZR060_SOS_IDX 0x07a
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#define ZR060_DRI_IDX 0x0c0
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#define ZR060_DQT_IDX 0x0cc
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#define ZR060_DHT_IDX 0x1d4
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#define ZR060_APP_IDX 0x380
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#define ZR060_COM_IDX 0x3c0
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/* ZR36060 LOAD register bits */
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#define ZR060_LOAD_Load (1 << 7)
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#define ZR060_LOAD_SyncRst (1 << 0)
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/* ZR36060 Code FIFO Status register bits */
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#define ZR060_CFSR_Busy (1 << 7)
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#define ZR060_CFSR_CBusy (1 << 2)
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#define ZR060_CFSR_CFIFO (3 << 0)
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/* ZR36060 Code Interface register */
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#define ZR060_CIR_Code16 (1 << 7)
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#define ZR060_CIR_Endian (1 << 6)
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#define ZR060_CIR_CFIS (1 << 2)
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#define ZR060_CIR_CodeMstr (1 << 0)
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/* ZR36060 Codec Mode register */
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#define ZR060_CMR_Comp (1 << 7)
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#define ZR060_CMR_ATP (1 << 6)
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#define ZR060_CMR_Pass2 (1 << 5)
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#define ZR060_CMR_TLM (1 << 4)
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#define ZR060_CMR_BRB (1 << 2)
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#define ZR060_CMR_FSF (1 << 1)
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/* ZR36060 Markers Enable register */
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#define ZR060_MER_App (1 << 7)
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#define ZR060_MER_Com (1 << 6)
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#define ZR060_MER_DRI (1 << 5)
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#define ZR060_MER_DQT (1 << 4)
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#define ZR060_MER_DHT (1 << 3)
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/* ZR36060 Interrupt Mask register */
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#define ZR060_IMR_EOAV (1 << 3)
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#define ZR060_IMR_EOI (1 << 2)
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#define ZR060_IMR_End (1 << 1)
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#define ZR060_IMR_DataErr (1 << 0)
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/* ZR36060 Interrupt Status register */
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#define ZR060_ISR_ProCnt (3 << 6)
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#define ZR060_ISR_EOAV (1 << 3)
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#define ZR060_ISR_EOI (1 << 2)
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#define ZR060_ISR_End (1 << 1)
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#define ZR060_ISR_DataErr (1 << 0)
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/* ZR36060 Video Control register */
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#define ZR060_VCR_Video8 (1 << 7)
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#define ZR060_VCR_Range (1 << 6)
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#define ZR060_VCR_FIDet (1 << 3)
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#define ZR060_VCR_FIVedge (1 << 2)
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#define ZR060_VCR_FIExt (1 << 1)
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#define ZR060_VCR_SyncMstr (1 << 0)
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/* ZR36060 Video Polarity register */
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#define ZR060_VPR_VCLKPol (1 << 7)
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#define ZR060_VPR_PValPol (1 << 6)
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#define ZR060_VPR_PoePol (1 << 5)
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#define ZR060_VPR_SImgPol (1 << 4)
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#define ZR060_VPR_BLPol (1 << 3)
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#define ZR060_VPR_FIPol (1 << 2)
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#define ZR060_VPR_HSPol (1 << 1)
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#define ZR060_VPR_VSPol (1 << 0)
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/* ZR36060 Scaling register */
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#define ZR060_SR_VScale (1 << 2)
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#define ZR060_SR_HScale2 (1 << 0)
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#define ZR060_SR_HScale4 (2 << 0)
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#endif /*fndef ZR36060_H */
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