c24b31147a
Merge irq-pxa168 and irq-mmp2. And support device tree also. Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from NR_IRQS_LEGACY. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
26 lines
716 B
ArmAsm
26 lines
716 B
ArmAsm
/*
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* linux/arch/arm/mach-mmp/include/mach/entry-macro.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/irq.h>
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#include <mach/regs-icu.h>
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.macro get_irqnr_preamble, base, tmp
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mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
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and \tmp, \tmp, #0xff00
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cmp \tmp, #0x5800
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ldr \base, =mmp_icu_base
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ldr \base, [\base, #0]
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addne \base, \base, #0x10c @ PJ1 AP INT SEL register
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addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \tmp, [\base, #0]
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and \irqnr, \tmp, #0x3f
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tst \tmp, #(1 << 6)
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.endm
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