47dd7a540b
This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers (Synopsys IP blocks). Driver documentation: o http://stlinux.com/drupal/kernel/network/stmmac Revisions: o http://stlinux.com/drupal/kernel/network/stmmac-driver-revisions Performances: o http://stlinux.com/drupal/benchmarks/networking/stmmac Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
693 lines
19 KiB
C
693 lines
19 KiB
C
/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/netdevice.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include "stmmac.h"
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#include "gmac.h"
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#undef GMAC_DEBUG
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/*#define GMAC_DEBUG*/
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#undef FRAME_FILTER_DEBUG
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/*#define FRAME_FILTER_DEBUG*/
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#ifdef GMAC_DEBUG
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#define DBG(fmt, args...) printk(fmt, ## args)
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#else
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#define DBG(fmt, args...) do { } while (0)
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#endif
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static void gmac_dump_regs(unsigned long ioaddr)
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{
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int i;
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pr_info("\t----------------------------------------------\n"
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"\t GMAC registers (base addr = 0x%8x)\n"
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"\t----------------------------------------------\n",
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(unsigned int)ioaddr);
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for (i = 0; i < 55; i++) {
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int offset = i * 4;
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pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
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offset, readl(ioaddr + offset));
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}
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return;
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}
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static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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/* DMA SW reset */
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value |= DMA_BUS_MODE_SFT_RESET;
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writel(value, ioaddr + DMA_BUS_MODE);
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do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
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value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
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((pbl << DMA_BUS_MODE_PBL_SHIFT) |
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(pbl << DMA_BUS_MODE_RPBL_SHIFT));
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#ifdef CONFIG_STMMAC_DA
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value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
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#endif
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writel(value, ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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/* The base address of the RX/TX descriptor lists must be written into
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* DMA CSR3 and CSR4, respectively. */
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writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
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writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
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return 0;
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}
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/* Transmit FIFO flush operation */
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static void gmac_flush_tx_fifo(unsigned long ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode,
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int rxmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (txmode == SF_DMA_MODE) {
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DBG(KERN_DEBUG "GMAC: enabling TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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csr6 |= DMA_CONTROL_TSF;
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/* Operating on second frame increase the performance
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* especially when transmit store-and-forward is used.*/
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csr6 |= DMA_CONTROL_OSF;
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} else {
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DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
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" (threshold = %d)\n", txmode);
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csr6 &= ~DMA_CONTROL_TSF;
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csr6 &= DMA_CONTROL_TC_TX_MASK;
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/* Set the transmit threashold */
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if (txmode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (txmode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else if (txmode <= 128)
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csr6 |= DMA_CONTROL_TTC_128;
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else if (txmode <= 192)
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csr6 |= DMA_CONTROL_TTC_192;
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else
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csr6 |= DMA_CONTROL_TTC_256;
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}
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if (rxmode == SF_DMA_MODE) {
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DBG(KERN_DEBUG "GMAC: enabling RX store and forward mode\n");
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csr6 |= DMA_CONTROL_RSF;
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} else {
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DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
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" (threshold = %d)\n", rxmode);
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csr6 &= ~DMA_CONTROL_RSF;
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csr6 &= DMA_CONTROL_TC_RX_MASK;
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if (rxmode <= 32)
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csr6 |= DMA_CONTROL_RTC_32;
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else if (rxmode <= 64)
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csr6 |= DMA_CONTROL_RTC_64;
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else if (rxmode <= 96)
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csr6 |= DMA_CONTROL_RTC_96;
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else
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csr6 |= DMA_CONTROL_RTC_128;
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}
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writel(csr6, ioaddr + DMA_CONTROL);
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return;
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}
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/* Not yet implemented --- no RMON module */
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static void gmac_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
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unsigned long ioaddr)
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{
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return;
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}
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static void gmac_dump_dma_regs(unsigned long ioaddr)
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{
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int i;
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pr_info(" DMA registers\n");
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for (i = 0; i < 22; i++) {
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if ((i < 9) || (i > 17)) {
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int offset = i * 4;
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pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
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(DMA_BUS_MODE + offset),
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readl(ioaddr + DMA_BUS_MODE + offset));
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}
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}
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return;
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}
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static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, unsigned long ioaddr)
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{
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int ret = 0;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.etx.error_summary)) {
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DBG(KERN_ERR "GMAC TX error... 0x%08x\n", p->des01.etx);
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if (unlikely(p->des01.etx.jabber_timeout)) {
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DBG(KERN_ERR "\tjabber_timeout error\n");
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x->tx_jabber++;
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}
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if (unlikely(p->des01.etx.frame_flushed)) {
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DBG(KERN_ERR "\tframe_flushed error\n");
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x->tx_frame_flushed++;
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gmac_flush_tx_fifo(ioaddr);
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}
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if (unlikely(p->des01.etx.loss_carrier)) {
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DBG(KERN_ERR "\tloss_carrier error\n");
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.etx.no_carrier)) {
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DBG(KERN_ERR "\tno_carrier error\n");
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.etx.late_collision)) {
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DBG(KERN_ERR "\tlate_collision error\n");
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stats->collisions += p->des01.etx.collision_count;
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}
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if (unlikely(p->des01.etx.excessive_collisions)) {
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DBG(KERN_ERR "\texcessive_collisions\n");
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stats->collisions += p->des01.etx.collision_count;
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}
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if (unlikely(p->des01.etx.excessive_deferral)) {
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DBG(KERN_INFO "\texcessive tx_deferral\n");
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x->tx_deferred++;
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}
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if (unlikely(p->des01.etx.underflow_error)) {
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DBG(KERN_ERR "\tunderflow error\n");
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gmac_flush_tx_fifo(ioaddr);
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x->tx_underflow++;
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}
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if (unlikely(p->des01.etx.ip_header_error)) {
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DBG(KERN_ERR "\tTX IP header csum error\n");
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x->tx_ip_header_error++;
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}
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if (unlikely(p->des01.etx.payload_error)) {
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DBG(KERN_ERR "\tAddr/Payload csum error\n");
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x->tx_payload_error++;
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gmac_flush_tx_fifo(ioaddr);
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}
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ret = -1;
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}
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if (unlikely(p->des01.etx.deferred)) {
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DBG(KERN_INFO "GMAC TX status: tx deferred\n");
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x->tx_deferred++;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.etx.vlan_frame) {
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DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
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x->tx_vlan++;
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}
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#endif
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return ret;
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}
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static int gmac_get_tx_len(struct dma_desc *p)
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{
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return p->des01.etx.buffer1_size;
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}
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static int gmac_coe_rdes0(int ipc_err, int type, int payload_err)
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{
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int ret = good_frame;
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u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
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/* bits 5 7 0 | Frame status
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* ----------------------------------------------------------
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* 0 0 0 | IEEE 802.3 Type frame (lenght < 1536 octects)
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* 1 0 0 | IPv4/6 No CSUM errorS.
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* 1 0 1 | IPv4/6 CSUM PAYLOAD error
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* 1 1 0 | IPv4/6 CSUM IP HR error
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* 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
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* 0 0 1 | IPv4/6 unsupported IP PAYLOAD
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* 0 1 1 | COE bypassed.. no IPv4/6 frame
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* 0 1 0 | Reserved.
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*/
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if (status == 0x0) {
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DBG(KERN_INFO "RX Des0 status: IEEE 802.3 Type frame.\n");
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ret = good_frame;
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} else if (status == 0x4) {
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DBG(KERN_INFO "RX Des0 status: IPv4/6 No CSUM errorS.\n");
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ret = good_frame;
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} else if (status == 0x5) {
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DBG(KERN_ERR "RX Des0 status: IPv4/6 Payload Error.\n");
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ret = csum_none;
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} else if (status == 0x6) {
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DBG(KERN_ERR "RX Des0 status: IPv4/6 Header Error.\n");
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ret = csum_none;
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} else if (status == 0x7) {
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DBG(KERN_ERR
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"RX Des0 status: IPv4/6 Header and Payload Error.\n");
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ret = csum_none;
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} else if (status == 0x1) {
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DBG(KERN_ERR
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"RX Des0 status: IPv4/6 unsupported IP PAYLOAD.\n");
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ret = discard_frame;
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} else if (status == 0x3) {
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DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
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ret = discard_frame;
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}
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return ret;
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}
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static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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int ret = good_frame;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.erx.error_summary)) {
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DBG(KERN_ERR "GMAC RX Error Summary... 0x%08x\n", p->des01.erx);
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if (unlikely(p->des01.erx.descriptor_error)) {
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DBG(KERN_ERR "\tdescriptor error\n");
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x->rx_desc++;
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stats->rx_length_errors++;
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}
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if (unlikely(p->des01.erx.overflow_error)) {
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DBG(KERN_ERR "\toverflow error\n");
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x->rx_gmac_overflow++;
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}
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if (unlikely(p->des01.erx.ipc_csum_error))
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DBG(KERN_ERR "\tIPC Csum Error/Giant frame\n");
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if (unlikely(p->des01.erx.late_collision)) {
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DBG(KERN_ERR "\tlate_collision error\n");
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stats->collisions++;
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stats->collisions++;
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}
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if (unlikely(p->des01.erx.receive_watchdog)) {
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DBG(KERN_ERR "\treceive_watchdog error\n");
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x->rx_watchdog++;
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}
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if (unlikely(p->des01.erx.error_gmii)) {
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DBG(KERN_ERR "\tReceive Error\n");
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x->rx_mii++;
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}
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if (unlikely(p->des01.erx.crc_error)) {
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DBG(KERN_ERR "\tCRC error\n");
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x->rx_crc++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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/* After a payload csum error, the ES bit is set.
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* It doesn't match with the information reported into the databook.
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* At any rate, we need to understand if the CSUM hw computation is ok
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* and report this info to the upper layers. */
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ret = gmac_coe_rdes0(p->des01.erx.ipc_csum_error,
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p->des01.erx.frame_type, p->des01.erx.payload_csum_error);
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if (unlikely(p->des01.erx.dribbling)) {
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DBG(KERN_ERR "GMAC RX: dribbling error\n");
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.sa_filter_fail)) {
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DBG(KERN_ERR "GMAC RX : Source Address filter fail\n");
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x->sa_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.da_filter_fail)) {
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DBG(KERN_ERR "GMAC RX : Destination Address filter fail\n");
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x->da_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.length_error)) {
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DBG(KERN_ERR "GMAC RX: length_error error\n");
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x->rx_lenght++;
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ret = discard_frame;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.erx.vlan_tag) {
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DBG(KERN_INFO "GMAC RX: VLAN frame tagged\n");
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x->rx_vlan++;
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}
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#endif
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return ret;
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}
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static void gmac_irq_status(unsigned long ioaddr)
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{
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u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & mmc_tx_irq))
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DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_TX_INTR));
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if (unlikely(intr_status & mmc_rx_irq))
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DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_RX_INTR));
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if (unlikely(intr_status & mmc_rx_csum_offload_irq))
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DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
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if (unlikely(intr_status & pmt_irq)) {
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DBG(KERN_DEBUG "GMAC: received Magic frame\n");
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/* clear the PMT bits 5 and 6 by reading the PMT
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* status register. */
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readl(ioaddr + GMAC_PMT);
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}
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return;
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}
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static void gmac_core_init(unsigned long ioaddr)
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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value |= GMAC_CORE_INIT;
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writel(value, ioaddr + GMAC_CONTROL);
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/* STBus Bridge Configuration */
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/*writel(0xc5608, ioaddr + 0x00007000);*/
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/* Freeze MMC counters */
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writel(0x8, ioaddr + GMAC_MMC_CTRL);
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/* Mask GMAC interrupts */
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writel(0x207, ioaddr + GMAC_INT_MASK);
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#ifdef STMMAC_VLAN_TAG_USED
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/* Tag detection without filtering */
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writel(0x0, ioaddr + GMAC_VLAN_TAG);
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#endif
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return;
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}
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static void gmac_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void gmac_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void gmac_set_filter(struct net_device *dev)
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{
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unsigned long ioaddr = dev->base_addr;
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unsigned int value = 0;
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DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
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__func__, dev->mc_count, dev->uc_count);
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if (dev->flags & IFF_PROMISC)
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value = GMAC_FRAME_FILTER_PR;
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else if ((dev->mc_count > HASH_TABLE_SIZE)
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|| (dev->flags & IFF_ALLMULTI)) {
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value = GMAC_FRAME_FILTER_PM; /* pass all multi */
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writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
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} else if (dev->mc_count > 0) {
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int i;
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u32 mc_filter[2];
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struct dev_mc_list *mclist;
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/* Hash filter for multicast */
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value = GMAC_FRAME_FILTER_HMC;
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memset(mc_filter, 0, sizeof(mc_filter));
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for (i = 0, mclist = dev->mc_list;
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mclist && i < dev->mc_count; i++, mclist = mclist->next) {
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/* The upper 6 bits of the calculated CRC are used to
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index the contens of the hash table */
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int bit_nr =
|
|
bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
|
|
/* The most significant bit determines the register to
|
|
* use (H/L) while the other 5 bits determine the bit
|
|
* within the register. */
|
|
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
|
|
}
|
|
writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
|
|
writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
|
|
}
|
|
|
|
/* Handle multiple unicast addresses (perfect filtering)*/
|
|
if (dev->uc_count > GMAC_MAX_UNICAST_ADDRESSES)
|
|
/* Switch to promiscuous mode is more than 16 addrs
|
|
are required */
|
|
value |= GMAC_FRAME_FILTER_PR;
|
|
else {
|
|
int i;
|
|
struct dev_addr_list *uc_ptr = dev->uc_list;
|
|
|
|
for (i = 0; i < dev->uc_count; i++) {
|
|
gmac_set_umac_addr(ioaddr, uc_ptr->da_addr,
|
|
i + 1);
|
|
|
|
DBG(KERN_INFO "\t%d "
|
|
"- Unicast addr %02x:%02x:%02x:%02x:%02x:"
|
|
"%02x\n", i + 1,
|
|
uc_ptr->da_addr[0], uc_ptr->da_addr[1],
|
|
uc_ptr->da_addr[2], uc_ptr->da_addr[3],
|
|
uc_ptr->da_addr[4], uc_ptr->da_addr[5]);
|
|
uc_ptr = uc_ptr->next;
|
|
}
|
|
}
|
|
|
|
#ifdef FRAME_FILTER_DEBUG
|
|
/* Enable Receive all mode (to debug filtering_fail errors) */
|
|
value |= GMAC_FRAME_FILTER_RA;
|
|
#endif
|
|
writel(value, ioaddr + GMAC_FRAME_FILTER);
|
|
|
|
DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
|
|
"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
|
|
readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
|
|
|
|
return;
|
|
}
|
|
|
|
static void gmac_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
|
|
unsigned int fc, unsigned int pause_time)
|
|
{
|
|
unsigned int flow = 0;
|
|
|
|
DBG(KERN_DEBUG "GMAC Flow-Control:\n");
|
|
if (fc & FLOW_RX) {
|
|
DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
|
|
flow |= GMAC_FLOW_CTRL_RFE;
|
|
}
|
|
if (fc & FLOW_TX) {
|
|
DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
|
|
flow |= GMAC_FLOW_CTRL_TFE;
|
|
}
|
|
|
|
if (duplex) {
|
|
DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
|
|
flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
|
|
}
|
|
|
|
writel(flow, ioaddr + GMAC_FLOW_CTRL);
|
|
return;
|
|
}
|
|
|
|
static void gmac_pmt(unsigned long ioaddr, unsigned long mode)
|
|
{
|
|
unsigned int pmt = 0;
|
|
|
|
if (mode == WAKE_MAGIC) {
|
|
DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
|
|
pmt |= power_down | magic_pkt_en;
|
|
} else if (mode == WAKE_UCAST) {
|
|
DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
|
|
pmt |= global_unicast;
|
|
}
|
|
|
|
writel(pmt, ioaddr + GMAC_PMT);
|
|
return;
|
|
}
|
|
|
|
static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
|
|
int disable_rx_ic)
|
|
{
|
|
int i;
|
|
for (i = 0; i < ring_size; i++) {
|
|
p->des01.erx.own = 1;
|
|
p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
|
|
/* To support jumbo frames */
|
|
p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
|
|
if (i == ring_size - 1)
|
|
p->des01.erx.end_ring = 1;
|
|
if (disable_rx_ic)
|
|
p->des01.erx.disable_ic = 1;
|
|
p++;
|
|
}
|
|
return;
|
|
}
|
|
|
|
static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ring_size; i++) {
|
|
p->des01.etx.own = 0;
|
|
if (i == ring_size - 1)
|
|
p->des01.etx.end_ring = 1;
|
|
p++;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static int gmac_get_tx_owner(struct dma_desc *p)
|
|
{
|
|
return p->des01.etx.own;
|
|
}
|
|
|
|
static int gmac_get_rx_owner(struct dma_desc *p)
|
|
{
|
|
return p->des01.erx.own;
|
|
}
|
|
|
|
static void gmac_set_tx_owner(struct dma_desc *p)
|
|
{
|
|
p->des01.etx.own = 1;
|
|
}
|
|
|
|
static void gmac_set_rx_owner(struct dma_desc *p)
|
|
{
|
|
p->des01.erx.own = 1;
|
|
}
|
|
|
|
static int gmac_get_tx_ls(struct dma_desc *p)
|
|
{
|
|
return p->des01.etx.last_segment;
|
|
}
|
|
|
|
static void gmac_release_tx_desc(struct dma_desc *p)
|
|
{
|
|
int ter = p->des01.etx.end_ring;
|
|
|
|
memset(p, 0, sizeof(struct dma_desc));
|
|
p->des01.etx.end_ring = ter;
|
|
|
|
return;
|
|
}
|
|
|
|
static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
|
|
int csum_flag)
|
|
{
|
|
p->des01.etx.first_segment = is_fs;
|
|
if (unlikely(len > BUF_SIZE_4KiB)) {
|
|
p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
|
|
p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
|
|
} else {
|
|
p->des01.etx.buffer1_size = len;
|
|
}
|
|
if (likely(csum_flag))
|
|
p->des01.etx.checksum_insertion = cic_full;
|
|
}
|
|
|
|
static void gmac_clear_tx_ic(struct dma_desc *p)
|
|
{
|
|
p->des01.etx.interrupt = 0;
|
|
}
|
|
|
|
static void gmac_close_tx_desc(struct dma_desc *p)
|
|
{
|
|
p->des01.etx.last_segment = 1;
|
|
p->des01.etx.interrupt = 1;
|
|
}
|
|
|
|
static int gmac_get_rx_frame_len(struct dma_desc *p)
|
|
{
|
|
return p->des01.erx.frame_length;
|
|
}
|
|
|
|
struct stmmac_ops gmac_driver = {
|
|
.core_init = gmac_core_init,
|
|
.dump_mac_regs = gmac_dump_regs,
|
|
.dma_init = gmac_dma_init,
|
|
.dump_dma_regs = gmac_dump_dma_regs,
|
|
.dma_mode = gmac_dma_operation_mode,
|
|
.dma_diagnostic_fr = gmac_dma_diagnostic_fr,
|
|
.tx_status = gmac_get_tx_frame_status,
|
|
.rx_status = gmac_get_rx_frame_status,
|
|
.get_tx_len = gmac_get_tx_len,
|
|
.set_filter = gmac_set_filter,
|
|
.flow_ctrl = gmac_flow_ctrl,
|
|
.pmt = gmac_pmt,
|
|
.init_rx_desc = gmac_init_rx_desc,
|
|
.init_tx_desc = gmac_init_tx_desc,
|
|
.get_tx_owner = gmac_get_tx_owner,
|
|
.get_rx_owner = gmac_get_rx_owner,
|
|
.release_tx_desc = gmac_release_tx_desc,
|
|
.prepare_tx_desc = gmac_prepare_tx_desc,
|
|
.clear_tx_ic = gmac_clear_tx_ic,
|
|
.close_tx_desc = gmac_close_tx_desc,
|
|
.get_tx_ls = gmac_get_tx_ls,
|
|
.set_tx_owner = gmac_set_tx_owner,
|
|
.set_rx_owner = gmac_set_rx_owner,
|
|
.get_rx_frame_len = gmac_get_rx_frame_len,
|
|
.host_irq_status = gmac_irq_status,
|
|
.set_umac_addr = gmac_set_umac_addr,
|
|
.get_umac_addr = gmac_get_umac_addr,
|
|
};
|
|
|
|
struct mac_device_info *gmac_setup(unsigned long ioaddr)
|
|
{
|
|
struct mac_device_info *mac;
|
|
u32 uid = readl(ioaddr + GMAC_VERSION);
|
|
|
|
pr_info("\tGMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
|
|
((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
|
|
|
|
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
|
|
|
|
mac->ops = &gmac_driver;
|
|
mac->hw.pmt = PMT_SUPPORTED;
|
|
mac->hw.link.port = GMAC_CONTROL_PS;
|
|
mac->hw.link.duplex = GMAC_CONTROL_DM;
|
|
mac->hw.link.speed = GMAC_CONTROL_FES;
|
|
mac->hw.mii.addr = GMAC_MII_ADDR;
|
|
mac->hw.mii.data = GMAC_MII_DATA;
|
|
|
|
return mac;
|
|
}
|