820 lines
23 KiB
C
820 lines
23 KiB
C
/**
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* Airgo MIMO wireless driver
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*
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* Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
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* Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
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* works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "agnx.h"
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#include "debug.h"
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#include "phy.h"
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unsigned int rx_frame_cnt = 0;
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//unsigned int local_tx_sent_cnt = 0;
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static inline void disable_rx_engine(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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iowrite32(0x100, ctl + AGNX_CIR_RXCTL);
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/* Wait for RX Control to have the Disable Rx Interrupt (0x100) set */
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ioread32(ctl + AGNX_CIR_RXCTL);
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}
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static inline void enable_rx_engine(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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iowrite32(0x80, ctl + AGNX_CIR_RXCTL);
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ioread32(ctl + AGNX_CIR_RXCTL);
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}
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inline void disable_rx_interrupt(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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u32 reg;
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disable_rx_engine(priv);
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reg = ioread32(ctl + AGNX_CIR_RXCFG);
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reg &= ~0x20;
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iowrite32(reg, ctl + AGNX_CIR_RXCFG);
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ioread32(ctl + AGNX_CIR_RXCFG);
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}
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inline void enable_rx_interrupt(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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u32 reg;
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reg = ioread32(ctl + AGNX_CIR_RXCFG);
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reg |= 0x20;
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iowrite32(reg, ctl + AGNX_CIR_RXCFG);
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ioread32(ctl + AGNX_CIR_RXCFG);
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enable_rx_engine(priv);
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}
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static inline void rx_desc_init(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_desc *desc = priv->rx.desc + idx;
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struct agnx_info *info = priv->rx.info + idx;
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memset(info, 0, sizeof(*info));
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info->dma_len = IEEE80211_MAX_RTS_THRESHOLD + sizeof(struct agnx_hdr);
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info->skb = dev_alloc_skb(info->dma_len);
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if (info->skb == NULL)
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agnx_bug("refill err");
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info->mapping = pci_map_single(priv->pdev, skb_tail_pointer(info->skb),
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info->dma_len, PCI_DMA_FROMDEVICE);
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memset(desc, 0, sizeof(*desc));
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desc->dma_addr = cpu_to_be32(info->mapping);
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/* Set the owner to the card */
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desc->frag = cpu_to_be32(be32_to_cpu(desc->frag) | OWNER);
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}
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static inline void rx_desc_reinit(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_info *info = priv->rx.info + idx;
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/* Cause ieee80211 will free the skb buffer, so we needn't to free it again?! */
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pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_FROMDEVICE);
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rx_desc_init(priv, idx);
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}
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static inline void rx_desc_reusing(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_desc *desc = priv->rx.desc + idx;
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struct agnx_info *info = priv->rx.info + idx;
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memset(desc, 0, sizeof(*desc));
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desc->dma_addr = cpu_to_be32(info->mapping);
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/* Set the owner to the card */
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desc->frag = cpu_to_be32(be32_to_cpu(desc->frag) | OWNER);
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}
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static void rx_desc_free(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_desc *desc = priv->rx.desc + idx;
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struct agnx_info *info = priv->rx.info + idx;
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BUG_ON(!desc || !info);
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if (info->mapping)
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pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_FROMDEVICE);
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if (info->skb)
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dev_kfree_skb(info->skb);
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memset(info, 0, sizeof(*info));
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memset(desc, 0, sizeof(*desc));
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}
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static inline void __tx_desc_free(struct agnx_priv *priv,
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struct agnx_desc *desc, struct agnx_info *info)
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{
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BUG_ON(!desc || !info);
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/* TODO make sure mapping, skb and len are consistency */
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if (info->mapping)
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pci_unmap_single(priv->pdev, info->mapping,
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info->dma_len, PCI_DMA_TODEVICE);
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if (info->type == PACKET)
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dev_kfree_skb(info->skb);
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memset(info, 0, sizeof(*info));
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memset(desc, 0, sizeof(*desc));
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}
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static void txm_desc_free(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_desc *desc = priv->txm.desc + idx;
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struct agnx_info *info = priv->txm.info + idx;
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__tx_desc_free(priv, desc, info);
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}
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static void txd_desc_free(struct agnx_priv *priv, unsigned int idx)
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{
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struct agnx_desc *desc = priv->txd.desc + idx;
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struct agnx_info *info = priv->txd.info + idx;
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__tx_desc_free(priv, desc, info);
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}
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int fill_rings(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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unsigned int i;
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u32 reg;
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AGNX_TRACE;
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priv->txd.idx_sent = priv->txm.idx_sent = 0;
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priv->rx.idx = priv->txm.idx = priv->txd.idx = 0;
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for (i = 0; i < priv->rx.size; i++)
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rx_desc_init(priv, i);
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for (i = 0; i < priv->txm.size; i++) {
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memset(priv->txm.desc + i, 0, sizeof(struct agnx_desc));
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memset(priv->txm.info + i, 0, sizeof(struct agnx_info));
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}
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for (i = 0; i < priv->txd.size; i++) {
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memset(priv->txd.desc + i, 0, sizeof(struct agnx_desc));
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memset(priv->txd.info + i, 0, sizeof(struct agnx_info));
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}
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/* FIXME Set the card RX TXM and TXD address */
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agnx_write32(ctl, AGNX_CIR_RXCMSTART, priv->rx.dma);
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agnx_write32(ctl, AGNX_CIR_RXCMEND, priv->txm.dma);
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agnx_write32(ctl, AGNX_CIR_TXMSTART, priv->txm.dma);
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agnx_write32(ctl, AGNX_CIR_TXMEND, priv->txd.dma);
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agnx_write32(ctl, AGNX_CIR_TXDSTART, priv->txd.dma);
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agnx_write32(ctl, AGNX_CIR_TXDEND, priv->txd.dma +
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sizeof(struct agnx_desc) * priv->txd.size);
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/* FIXME Relinquish control of rings to card */
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reg = agnx_read32(ctl, AGNX_CIR_BLKCTL);
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reg &= ~0x800;
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agnx_write32(ctl, AGNX_CIR_BLKCTL, reg);
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return 0;
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} /* fill_rings */
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void unfill_rings(struct agnx_priv *priv)
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{
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unsigned long flags;
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unsigned int i;
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AGNX_TRACE;
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spin_lock_irqsave(&priv->lock, flags);
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for (i = 0; i < priv->rx.size; i++)
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rx_desc_free(priv, i);
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for (i = 0; i < priv->txm.size; i++)
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txm_desc_free(priv, i);
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for (i = 0; i < priv->txd.size; i++)
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txd_desc_free(priv, i);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/* Extract the bitrate out of a CCK PLCP header.
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copy from bcm43xx driver */
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static inline u8 agnx_plcp_get_bitrate_cck(__be32 *phyhdr_11b)
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{
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/* FIXME */
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switch (*(u8 *)phyhdr_11b) {
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case 0x0A:
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return 0;
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case 0x14:
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return 1;
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case 0x37:
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return 2;
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case 0x6E:
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return 3;
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}
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agnx_bug("Wrong plcp rate");
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return 0;
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}
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/* FIXME */
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static inline u8 agnx_plcp_get_bitrate_ofdm(__be32 *phyhdr_11g)
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{
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u8 rate = *(u8 *)phyhdr_11g & 0xF;
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printk(PFX "G mode rate is 0x%x\n", rate);
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return rate;
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}
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/* FIXME */
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static void get_rx_stats(struct agnx_priv *priv, struct agnx_hdr *hdr,
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struct ieee80211_rx_status *stat)
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{
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void __iomem *ctl = priv->ctl;
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u8 *rssi;
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u32 noise;
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/* FIXME just for test */
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int snr = 40; /* signal-to-noise ratio */
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memset(stat, 0, sizeof(*stat));
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/* RSSI */
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rssi = (u8 *)&hdr->phy_stats_lo;
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// stat->ssi = (rssi[0] + rssi[1] + rssi[2]) / 3;
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/* Noise */
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noise = ioread32(ctl + AGNX_GCR_NOISE0);
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noise += ioread32(ctl + AGNX_GCR_NOISE1);
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noise += ioread32(ctl + AGNX_GCR_NOISE2);
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stat->noise = noise / 3;
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/* Signal quality */
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//snr = stat->ssi - stat->noise;
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if (snr >=0 && snr < 40)
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stat->signal = 5 * snr / 2;
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else if (snr >= 40)
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stat->signal = 100;
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else
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stat->signal = 0;
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if (hdr->_11b0 && !hdr->_11g0) {
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stat->rate_idx = agnx_plcp_get_bitrate_cck(&hdr->_11b0);
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} else if (!hdr->_11b0 && hdr->_11g0) {
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printk(PFX "RX: Found G mode packet\n");
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stat->rate_idx = agnx_plcp_get_bitrate_ofdm(&hdr->_11g0);
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} else
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agnx_bug("Unknown packets type");
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stat->band = IEEE80211_BAND_2GHZ;
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stat->freq = agnx_channels[priv->channel - 1].center_freq;
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// stat->antenna = 3;
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// stat->mactime = be32_to_cpu(hdr->time_stamp);
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// stat->channel = priv->channel;
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}
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static inline void combine_hdr_frag(struct ieee80211_hdr *ieeehdr,
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struct sk_buff *skb)
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{
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u16 fctl;
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unsigned int hdrlen;
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fctl = le16_to_cpu(ieeehdr->frame_control);
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hdrlen = ieee80211_hdrlen(fctl);
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/* FIXME */
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if (hdrlen < (2+2+6)/*minimum hdr*/ ||
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hdrlen > sizeof(struct ieee80211_mgmt)) {
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printk(KERN_ERR PFX "hdr len is %d\n", hdrlen);
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agnx_bug("Wrong ieee80211 hdr detected");
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}
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skb_push(skb, hdrlen);
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memcpy(skb->data, ieeehdr, hdrlen);
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} /* combine_hdr_frag */
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static inline int agnx_packet_check(struct agnx_priv *priv, struct agnx_hdr *agnxhdr,
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unsigned packet_len)
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{
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if (agnx_get_bits(CRC_FAIL, CRC_FAIL_SHIFT, be32_to_cpu(agnxhdr->reg1)) == 1){
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printk(PFX "RX: CRC check fail\n");
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goto drop;
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}
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if (packet_len > 2048) {
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printk(PFX "RX: Too long packet detected\n");
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goto drop;
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}
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/* FIXME Just usable for Promious Mode, for Manage mode exclude FCS */
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/* if (packet_len - sizeof(*agnxhdr) < FCS_LEN) { */
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/* printk(PFX "RX: Too short packet detected\n"); */
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/* goto drop; */
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/* } */
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return 0;
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drop:
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priv->stats.dot11FCSErrorCount++;
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return -1;
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}
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void handle_rx_irq(struct agnx_priv *priv)
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{
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struct ieee80211_rx_status status;
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unsigned int len;
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// AGNX_TRACE;
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do {
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struct agnx_desc *desc;
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u32 frag;
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struct agnx_info *info;
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struct agnx_hdr *hdr;
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struct sk_buff *skb;
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unsigned int i = priv->rx.idx % priv->rx.size;
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desc = priv->rx.desc + i;
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frag = be32_to_cpu(desc->frag);
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if (frag & OWNER)
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break;
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info = priv->rx.info + i;
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skb = info->skb;
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hdr = (struct agnx_hdr *)(skb->data);
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len = (frag & PACKET_LEN) >> PACKET_LEN_SHIFT;
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if (agnx_packet_check(priv, hdr, len) == -1) {
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rx_desc_reusing(priv, i);
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continue;
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}
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skb_put(skb, len);
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do {
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u16 fctl;
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fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr)->frame_control);
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if ((fctl & IEEE80211_FCTL_STYPE) != IEEE80211_STYPE_BEACON)// && !(fctl & IEEE80211_STYPE_BEACON))
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dump_ieee80211_hdr((struct ieee80211_hdr *)hdr->mac_hdr, "RX");
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} while (0);
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if (hdr->_11b0 && !hdr->_11g0) {
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/* int j; */
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/* u16 fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr) */
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/* ->frame_control); */
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/* if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) { */
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/* agnx_print_rx_hdr(hdr); */
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// agnx_print_sta(priv, BSSID_STAID);
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/* for (j = 0; j < 8; j++) */
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/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */
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/* } */
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get_rx_stats(priv, hdr, &status);
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skb_pull(skb, sizeof(*hdr));
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combine_hdr_frag((struct ieee80211_hdr *)hdr->mac_hdr, skb);
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} else if (!hdr->_11b0 && hdr->_11g0) {
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// int j;
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agnx_print_rx_hdr(hdr);
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agnx_print_sta(priv, BSSID_STAID);
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// for (j = 0; j < 8; j++)
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agnx_print_sta_tx_wq(priv, BSSID_STAID, 0);
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print_hex_dump_bytes("agnx: RX_PACKET: ", DUMP_PREFIX_NONE,
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skb->data, skb->len + 8);
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// if (agnx_plcp_get_bitrate_ofdm(&hdr->_11g0) == 0)
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get_rx_stats(priv, hdr, &status);
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skb_pull(skb, sizeof(*hdr));
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combine_hdr_frag((struct ieee80211_hdr *)
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((void *)&hdr->mac_hdr), skb);
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// dump_ieee80211_hdr((struct ieee80211_hdr *)skb->data, "RX G");
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} else
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agnx_bug("Unknown packets type");
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ieee80211_rx_irqsafe(priv->hw, skb, &status);
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rx_desc_reinit(priv, i);
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} while ( priv->rx.idx++ );
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} /* handle_rx_irq */
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static inline void handle_tx_irq(struct agnx_priv *priv, struct agnx_ring *ring)
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{
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struct agnx_desc *desc;
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struct agnx_info *info;
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unsigned int idx;
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for (idx = ring->idx_sent; idx < ring->idx; idx++) {
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unsigned int i = idx % ring->size;
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u32 frag;
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desc = ring->desc + i;
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info = ring->info + i;
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frag = be32_to_cpu(desc->frag);
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if (frag & OWNER) {
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if (info->type == HEADER)
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break;
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else
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agnx_bug("TX error");
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}
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pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_TODEVICE);
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do {
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// int j;
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size_t len;
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len = info->skb->len - sizeof(struct agnx_hdr) + info->hdr_len;
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// if (len == 614) {
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// agnx_print_desc(desc);
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if (info->type == PACKET) {
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// agnx_print_tx_hdr((struct agnx_hdr *)info->skb->data);
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/* agnx_print_sta_power(priv, LOCAL_STAID); */
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/* agnx_print_sta(priv, LOCAL_STAID); */
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/* // for (j = 0; j < 8; j++) */
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/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, 0); */
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// agnx_print_sta_power(priv, BSSID_STAID);
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// agnx_print_sta(priv, BSSID_STAID);
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// for (j = 0; j < 8; j++)
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// agnx_print_sta_tx_wq(priv, BSSID_STAID, 0);
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}
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// }
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} while (0);
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if (info->type == PACKET) {
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// dump_txm_registers(priv);
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// dump_rxm_registers(priv);
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// dump_bm_registers(priv);
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// dump_cir_registers(priv);
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}
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if (info->type == PACKET) {
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// struct ieee80211_hdr *hdr;
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struct ieee80211_tx_info *txi = IEEE80211_SKB_CB(info->skb);
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skb_pull(info->skb, sizeof(struct agnx_hdr));
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memcpy(skb_push(info->skb, info->hdr_len), &info->hdr, info->hdr_len);
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// dump_ieee80211_hdr((struct ieee80211_hdr *)info->skb->data, "TX_HANDLE");
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/* print_hex_dump_bytes("agnx: TX_HANDLE: ", DUMP_PREFIX_NONE, */
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/* info->skb->data, info->skb->len); */
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if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK))
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txi->flags |= IEEE80211_TX_STAT_ACK;
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ieee80211_tx_status_irqsafe(priv->hw, info->skb);
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/* info->tx_status.queue_number = (ring->size - i) / 2; */
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/* ieee80211_tx_status_irqsafe(priv->hw, info->skb, &(info->tx_status)); */
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/* } else */
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/* dev_kfree_skb_irq(info->skb); */
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}
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memset(desc, 0, sizeof(*desc));
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memset(info, 0, sizeof(*info));
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}
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|
|
ring->idx_sent = idx;
|
|
/* TODO fill the priv->low_level_stats */
|
|
|
|
/* ieee80211_wake_queue(priv->hw, 0); */
|
|
}
|
|
|
|
void handle_txm_irq(struct agnx_priv *priv)
|
|
{
|
|
handle_tx_irq(priv, &priv->txm);
|
|
}
|
|
|
|
void handle_txd_irq(struct agnx_priv *priv)
|
|
{
|
|
handle_tx_irq(priv, &priv->txd);
|
|
}
|
|
|
|
void handle_other_irq(struct agnx_priv *priv)
|
|
{
|
|
// void __iomem *ctl = priv->ctl;
|
|
u32 status = priv->irq_status;
|
|
void __iomem *ctl = priv->ctl;
|
|
u32 reg;
|
|
|
|
if (status & IRQ_TX_BEACON) {
|
|
iowrite32(IRQ_TX_BEACON, ctl + AGNX_INT_STAT);
|
|
printk(PFX "IRQ: TX Beacon control is 0X%.8X\n", ioread32(ctl + AGNX_TXM_BEACON_CTL));
|
|
printk(PFX "IRQ: TX Beacon rx frame num: %d\n", rx_frame_cnt);
|
|
}
|
|
if (status & IRQ_TX_RETRY) {
|
|
reg = ioread32(ctl + AGNX_TXM_RETRYSTAID);
|
|
printk(PFX "IRQ: TX Retry, RETRY STA ID is %x\n", reg);
|
|
}
|
|
if (status & IRQ_TX_ACTIVITY)
|
|
printk(PFX "IRQ: TX Activity\n");
|
|
if (status & IRQ_RX_ACTIVITY)
|
|
printk(PFX "IRQ: RX Activity\n");
|
|
if (status & IRQ_RX_X)
|
|
printk(PFX "IRQ: RX X\n");
|
|
if (status & IRQ_RX_Y) {
|
|
reg = ioread32(ctl + AGNX_INT_MASK);
|
|
reg &= ~IRQ_RX_Y;
|
|
iowrite32(reg, ctl + AGNX_INT_MASK);
|
|
iowrite32(IRQ_RX_Y, ctl + AGNX_INT_STAT);
|
|
printk(PFX "IRQ: RX Y\n");
|
|
}
|
|
if (status & IRQ_RX_HASHHIT) {
|
|
reg = ioread32(ctl + AGNX_INT_MASK);
|
|
reg &= ~IRQ_RX_HASHHIT;
|
|
iowrite32(reg, ctl + AGNX_INT_MASK);
|
|
iowrite32(IRQ_RX_HASHHIT, ctl + AGNX_INT_STAT);
|
|
printk(PFX "IRQ: RX Hash Hit\n");
|
|
|
|
}
|
|
if (status & IRQ_RX_FRAME) {
|
|
reg = ioread32(ctl + AGNX_INT_MASK);
|
|
reg &= ~IRQ_RX_FRAME;
|
|
iowrite32(reg, ctl + AGNX_INT_MASK);
|
|
iowrite32(IRQ_RX_FRAME, ctl + AGNX_INT_STAT);
|
|
printk(PFX "IRQ: RX Frame\n");
|
|
rx_frame_cnt++;
|
|
}
|
|
if (status & IRQ_ERR_INT) {
|
|
iowrite32(IRQ_ERR_INT, ctl + AGNX_INT_STAT);
|
|
// agnx_hw_reset(priv);
|
|
printk(PFX "IRQ: Error Interrupt\n");
|
|
}
|
|
if (status & IRQ_TX_QUE_FULL)
|
|
printk(PFX "IRQ: TX Workqueue Full\n");
|
|
if (status & IRQ_BANDMAN_ERR)
|
|
printk(PFX "IRQ: Bandwidth Management Error\n");
|
|
if (status & IRQ_TX_DISABLE)
|
|
printk(PFX "IRQ: TX Disable\n");
|
|
if (status & IRQ_RX_IVASESKEY)
|
|
printk(PFX "IRQ: RX Invalid Session Key\n");
|
|
if (status & IRQ_REP_THHIT)
|
|
printk(PFX "IRQ: Replay Threshold Hit\n");
|
|
if (status & IRQ_TIMER1)
|
|
printk(PFX "IRQ: Timer1\n");
|
|
if (status & IRQ_TIMER_CNT)
|
|
printk(PFX "IRQ: Timer Count\n");
|
|
if (status & IRQ_PHY_FASTINT)
|
|
printk(PFX "IRQ: Phy Fast Interrupt\n");
|
|
if (status & IRQ_PHY_SLOWINT)
|
|
printk(PFX "IRQ: Phy Slow Interrupt\n");
|
|
if (status & IRQ_OTHER)
|
|
printk(PFX "IRQ: 0x80000000\n");
|
|
} /* handle_other_irq */
|
|
|
|
|
|
static inline void route_flag_set(struct agnx_hdr *txhdr)
|
|
{
|
|
// u32 reg = 0;
|
|
|
|
/* FIXME */
|
|
/* reg = (0x7 << ROUTE_COMPRESSION_SHIFT) & ROUTE_COMPRESSION; */
|
|
/* txhdr->reg5 = cpu_to_be32(reg); */
|
|
txhdr->reg5 = (0xa << 0x0) | (0x7 << 0x18);
|
|
// txhdr->reg5 = cpu_to_be32((0xa << 0x0) | (0x7 << 0x18));
|
|
// txhdr->reg5 = cpu_to_be32(0x7 << 0x0);
|
|
}
|
|
|
|
/* Return 0 if no match */
|
|
static inline unsigned int get_power_level(unsigned int rate, unsigned int antennas_num)
|
|
{
|
|
unsigned int power_level;
|
|
|
|
switch (rate) {
|
|
case 10:
|
|
case 20:
|
|
case 55:
|
|
case 60:
|
|
case 90:
|
|
case 120: power_level = 22; break;
|
|
case 180: power_level = 19; break;
|
|
case 240: power_level = 18; break;
|
|
case 360: power_level = 16; break;
|
|
case 480: power_level = 15; break;
|
|
case 540: power_level = 14; break;
|
|
default:
|
|
agnx_bug("Error rate setting\n");
|
|
}
|
|
|
|
if (power_level && (antennas_num == 2))
|
|
power_level -= 3;
|
|
|
|
return power_level;
|
|
}
|
|
|
|
static inline void fill_agnx_hdr(struct agnx_priv *priv, struct agnx_info *tx_info)
|
|
{
|
|
struct agnx_hdr *txhdr = (struct agnx_hdr *)tx_info->skb->data;
|
|
size_t len;
|
|
u16 fc = le16_to_cpu(*(__le16 *)&tx_info->hdr);
|
|
u32 reg;
|
|
|
|
memset(txhdr, 0, sizeof(*txhdr));
|
|
|
|
// reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, LOCAL_STAID);
|
|
reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, BSSID_STAID);
|
|
reg |= agnx_set_bits(WORKQUEUE_ID, WORKQUEUE_ID_SHIFT, 0);
|
|
txhdr->reg4 = cpu_to_be32(reg);
|
|
|
|
/* Set the Hardware Sequence Number to 1? */
|
|
reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 0);
|
|
// reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 1);
|
|
reg |= agnx_set_bits(MAC_HDR_LEN, MAC_HDR_LEN_SHIFT, tx_info->hdr_len);
|
|
txhdr->reg1 = cpu_to_be32(reg);
|
|
/* Set the agnx_hdr's MAC header */
|
|
memcpy(txhdr->mac_hdr, &tx_info->hdr, tx_info->hdr_len);
|
|
|
|
reg = agnx_set_bits(ACK, ACK_SHIFT, 1);
|
|
// reg = agnx_set_bits(ACK, ACK_SHIFT, 0);
|
|
reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 0);
|
|
// reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 1);
|
|
reg |= agnx_set_bits(RELAY, RELAY_SHIFT, 0);
|
|
reg |= agnx_set_bits(TM, TM_SHIFT, 0);
|
|
txhdr->reg0 = cpu_to_be32(reg);
|
|
|
|
/* Set the long and short retry limits */
|
|
txhdr->tx.short_retry_limit = tx_info->txi->control.rates[0].count;
|
|
txhdr->tx.long_retry_limit = tx_info->txi->control.rates[0].count;
|
|
|
|
/* FIXME */
|
|
len = tx_info->skb->len - sizeof(*txhdr) + tx_info->hdr_len + FCS_LEN;
|
|
if (fc & IEEE80211_FCTL_PROTECTED)
|
|
len += 8;
|
|
len = 2398;
|
|
reg = agnx_set_bits(FRAG_SIZE, FRAG_SIZE_SHIFT, len);
|
|
len = tx_info->skb->len - sizeof(*txhdr);
|
|
reg |= agnx_set_bits(PAYLOAD_LEN, PAYLOAD_LEN_SHIFT, len);
|
|
txhdr->reg3 = cpu_to_be32(reg);
|
|
|
|
route_flag_set(txhdr);
|
|
} /* fill_hdr */
|
|
|
|
static void txm_power_set(struct agnx_priv *priv,
|
|
struct ieee80211_tx_info *txi)
|
|
{
|
|
struct agnx_sta_power power;
|
|
u32 reg;
|
|
|
|
/* FIXME */
|
|
if (txi->control.rates[0].idx < 0) {
|
|
/* For B mode Short Preamble */
|
|
reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_SHORT);
|
|
// control->tx_rate = -control->tx_rate;
|
|
} else
|
|
reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211G);
|
|
// reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_LONG);
|
|
reg |= agnx_set_bits(SIGNAL, SIGNAL_SHIFT, 0xB);
|
|
reg |= agnx_set_bits(RATE, RATE_SHIFT, 0xB);
|
|
// reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 15);
|
|
reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 20);
|
|
/* if rate < 11M set it to 0 */
|
|
reg |= agnx_set_bits(NUM_TRANSMITTERS, NUM_TRANSMITTERS_SHIFT, 1);
|
|
// reg |= agnx_set_bits(EDCF, EDCF_SHIFT, 1);
|
|
// reg |= agnx_set_bits(TIFS, TIFS_SHIFT, 1);
|
|
|
|
power.reg = reg;
|
|
// power.reg = cpu_to_le32(reg);
|
|
|
|
// set_sta_power(priv, &power, LOCAL_STAID);
|
|
set_sta_power(priv, &power, BSSID_STAID);
|
|
}
|
|
|
|
static inline int tx_packet_check(struct sk_buff *skb)
|
|
{
|
|
unsigned int ieee_len = ieee80211_get_hdrlen_from_skb(skb);
|
|
if (skb->len > 2048) {
|
|
printk(KERN_ERR PFX "length is %d\n", skb->len);
|
|
agnx_bug("Too long TX skb");
|
|
return -1;
|
|
}
|
|
/* FIXME */
|
|
if (skb->len == ieee_len) {
|
|
printk(PFX "A strange TX packet\n");
|
|
return -1;
|
|
/* tx_faile_irqsafe(); */
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int __agnx_tx(struct agnx_priv *priv, struct sk_buff *skb,
|
|
struct agnx_ring *ring)
|
|
{
|
|
struct agnx_desc *hdr_desc, *frag_desc;
|
|
struct agnx_info *hdr_info, *frag_info;
|
|
struct ieee80211_tx_info *txi = IEEE80211_SKB_CB(skb);
|
|
unsigned long flags;
|
|
unsigned int i;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
/* The RX interrupt need be Disable until this TX packet
|
|
is handled in the next tx interrupt */
|
|
disable_rx_interrupt(priv);
|
|
|
|
i = ring->idx;
|
|
ring->idx += 2;
|
|
/* if (priv->txm_idx - priv->txm_idx_sent == AGNX_TXM_RING_SIZE - 2) */
|
|
/* ieee80211_stop_queue(priv->hw, 0); */
|
|
|
|
/* Set agnx header's info and desc */
|
|
i %= ring->size;
|
|
hdr_desc = ring->desc + i;
|
|
hdr_info = ring->info + i;
|
|
hdr_info->hdr_len = ieee80211_get_hdrlen_from_skb(skb);
|
|
memcpy(&hdr_info->hdr, skb->data, hdr_info->hdr_len);
|
|
|
|
/* Add the agnx header to the front of the SKB */
|
|
skb_push(skb, sizeof(struct agnx_hdr) - hdr_info->hdr_len);
|
|
|
|
hdr_info->txi = txi;
|
|
hdr_info->dma_len = sizeof(struct agnx_hdr);
|
|
hdr_info->skb = skb;
|
|
hdr_info->type = HEADER;
|
|
fill_agnx_hdr(priv, hdr_info);
|
|
hdr_info->mapping = pci_map_single(priv->pdev, skb->data,
|
|
hdr_info->dma_len, PCI_DMA_TODEVICE);
|
|
do {
|
|
u32 frag = 0;
|
|
frag |= agnx_set_bits(FIRST_FRAG, FIRST_FRAG_SHIFT, 1);
|
|
frag |= agnx_set_bits(LAST_FRAG, LAST_FRAG_SHIFT, 0);
|
|
frag |= agnx_set_bits(PACKET_LEN, PACKET_LEN_SHIFT, skb->len);
|
|
frag |= agnx_set_bits(FIRST_FRAG_LEN, FIRST_FRAG_LEN_SHIFT, 1);
|
|
frag |= agnx_set_bits(OWNER, OWNER_SHIFT, 1);
|
|
hdr_desc->frag = cpu_to_be32(frag);
|
|
} while (0);
|
|
hdr_desc->dma_addr = cpu_to_be32(hdr_info->mapping);
|
|
|
|
|
|
/* Set Frag's info and desc */
|
|
i = (i + 1) % ring->size;
|
|
frag_desc = ring->desc + i;
|
|
frag_info = ring->info + i;
|
|
memcpy(frag_info, hdr_info, sizeof(struct agnx_info));
|
|
frag_info->type = PACKET;
|
|
frag_info->dma_len = skb->len - hdr_info->dma_len;
|
|
frag_info->mapping = pci_map_single(priv->pdev, skb->data + hdr_info->dma_len,
|
|
frag_info->dma_len, PCI_DMA_TODEVICE);
|
|
do {
|
|
u32 frag = 0;
|
|
frag |= agnx_set_bits(FIRST_FRAG, FIRST_FRAG_SHIFT, 0);
|
|
frag |= agnx_set_bits(LAST_FRAG, LAST_FRAG_SHIFT, 1);
|
|
frag |= agnx_set_bits(PACKET_LEN, PACKET_LEN_SHIFT, skb->len);
|
|
frag |= agnx_set_bits(SUB_FRAG_LEN, SUB_FRAG_LEN_SHIFT, frag_info->dma_len);
|
|
frag_desc->frag = cpu_to_be32(frag);
|
|
} while (0);
|
|
frag_desc->dma_addr = cpu_to_be32(frag_info->mapping);
|
|
|
|
txm_power_set(priv, txi);
|
|
|
|
/* do { */
|
|
/* int j; */
|
|
/* size_t len; */
|
|
/* len = skb->len - hdr_info->dma_len + hdr_info->hdr_len; */
|
|
/* // if (len == 614) { */
|
|
/* agnx_print_desc(hdr_desc); */
|
|
/* agnx_print_desc(frag_desc); */
|
|
/* agnx_print_tx_hdr((struct agnx_hdr *)skb->data); */
|
|
/* agnx_print_sta_power(priv, LOCAL_STAID); */
|
|
/* agnx_print_sta(priv, LOCAL_STAID); */
|
|
/* for (j = 0; j < 8; j++) */
|
|
/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, j); */
|
|
/* agnx_print_sta_power(priv, BSSID_STAID); */
|
|
/* agnx_print_sta(priv, BSSID_STAID); */
|
|
/* for (j = 0; j < 8; j++) */
|
|
/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */
|
|
/* // } */
|
|
/* } while (0); */
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
/* FIXME ugly code */
|
|
/* Trigger TXM */
|
|
do {
|
|
u32 reg;
|
|
reg = (ioread32(priv->ctl + AGNX_CIR_TXMCTL));
|
|
reg |= 0x8;
|
|
iowrite32((reg), priv->ctl + AGNX_CIR_TXMCTL);
|
|
}while (0);
|
|
|
|
/* Trigger TXD */
|
|
do {
|
|
u32 reg;
|
|
reg = (ioread32(priv->ctl + AGNX_CIR_TXDCTL));
|
|
reg |= 0x8;
|
|
iowrite32((reg), priv->ctl + AGNX_CIR_TXDCTL);
|
|
}while (0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb)
|
|
{
|
|
u16 fctl;
|
|
|
|
if (tx_packet_check(skb))
|
|
return 0;
|
|
|
|
/* print_hex_dump_bytes("agnx: TX_PACKET: ", DUMP_PREFIX_NONE, */
|
|
/* skb->data, skb->len); */
|
|
|
|
fctl = le16_to_cpu(*((__le16 *)skb->data));
|
|
|
|
if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA )
|
|
return __agnx_tx(priv, skb, &priv->txd);
|
|
else
|
|
return __agnx_tx(priv, skb, &priv->txm);
|
|
}
|