77 lines
3.5 KiB
C
77 lines
3.5 KiB
C
/*
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* MMUAccInt.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef _MMU_ACC_INT_H
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#define _MMU_ACC_INT_H
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/* Mappings of level 1 EASI function numbers to function names */
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#define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3)
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#define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17)
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#define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39)
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#define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51)
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#define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102)
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#define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103)
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#define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156)
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#define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174)
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#define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180)
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#define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190)
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#define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194)
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#define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198)
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#define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203)
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#define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204)
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#define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205)
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#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209)
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#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211)
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#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212)
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#define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213)
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#define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214)
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#define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226)
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#define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268)
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#define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322)
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/* Register offset address definitions */
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#define MMU_MMU_SYSCONFIG_OFFSET 0x10
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#define MMU_MMU_IRQSTATUS_OFFSET 0x18
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#define MMU_MMU_IRQENABLE_OFFSET 0x1c
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#define MMU_MMU_WALKING_ST_OFFSET 0x40
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#define MMU_MMU_CNTL_OFFSET 0x44
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#define MMU_MMU_FAULT_AD_OFFSET 0x48
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#define MMU_MMU_TTB_OFFSET 0x4c
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#define MMU_MMU_LOCK_OFFSET 0x50
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#define MMU_MMU_LD_TLB_OFFSET 0x54
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#define MMU_MMU_CAM_OFFSET 0x58
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#define MMU_MMU_RAM_OFFSET 0x5c
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#define MMU_MMU_GFLUSH_OFFSET 0x60
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#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
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/* Bitfield mask and offset declarations */
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#define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18
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#define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3
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#define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1
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#define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0
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#define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1
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#define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0
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#define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4
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#define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2
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#define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2
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#define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1
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#define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00
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#define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10
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#define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0
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#define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4
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#endif /* _MMU_ACC_INT_H */
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