423 lines
9.6 KiB
C
423 lines
9.6 KiB
C
/*
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* clk.c
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Clock and Timer services.
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#include <linux/types.h>
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/* ----------------------------------- Host OS */
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#include <dspbridge/host_os.h>
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#include <plat/dmtimer.h>
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#include <plat/mcbsp.h>
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/* ----------------------------------- DSP/BIOS Bridge */
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#include <dspbridge/dbdefs.h>
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#include <dspbridge/cfg.h>
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#include <dspbridge/drv.h>
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#include <dspbridge/dev.h>
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#include "_tiomap.h"
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/* ----------------------------------- Trace & Debug */
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#include <dspbridge/dbc.h>
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/* ----------------------------------- This */
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#include <dspbridge/clk.h>
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/* ----------------------------------- Defines, Data Structures, Typedefs */
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#define OMAP_SSI_OFFSET 0x58000
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#define OMAP_SSI_SIZE 0x1000
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#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
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#define SSI_AUTOIDLE (1 << 0)
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#define SSI_SIDLE_SMARTIDLE (2 << 3)
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#define SSI_MIDLE_NOIDLE (1 << 12)
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/* Clk types requested by the dsp */
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#define IVA2_CLK 0
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#define GPT_CLK 1
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#define WDT_CLK 2
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#define MCBSP_CLK 3
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#define SSI_CLK 4
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/* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
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#define DMT_ID(id) ((id) + 4)
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/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
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#define MCBSP_ID(id) ((id) - 6)
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static struct omap_dm_timer *timer[4];
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struct clk *iva2_clk;
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struct dsp_ssi {
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struct clk *sst_fck;
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struct clk *ssr_fck;
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struct clk *ick;
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};
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static struct dsp_ssi ssi;
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static u32 dsp_clocks;
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static inline u32 is_dsp_clk_active(u32 clk, u8 id)
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{
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return clk & (1 << id);
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}
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static inline void set_dsp_clk_active(u32 *clk, u8 id)
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{
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*clk |= (1 << id);
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}
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static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
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{
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*clk &= ~(1 << id);
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}
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static s8 get_clk_type(u8 id)
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{
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s8 type;
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if (id == DSP_CLK_IVA2)
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type = IVA2_CLK;
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else if (id <= DSP_CLK_GPT8)
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type = GPT_CLK;
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else if (id == DSP_CLK_WDT3)
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type = WDT_CLK;
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else if (id <= DSP_CLK_MCBSP5)
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type = MCBSP_CLK;
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else if (id == DSP_CLK_SSI)
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type = SSI_CLK;
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else
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type = -1;
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return type;
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}
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/*
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* ======== dsp_clk_exit ========
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* Purpose:
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* Cleanup CLK module.
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*/
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void dsp_clk_exit(void)
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{
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dsp_clock_disable_all(dsp_clocks);
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clk_put(iva2_clk);
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clk_put(ssi.sst_fck);
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clk_put(ssi.ssr_fck);
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clk_put(ssi.ick);
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}
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/*
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* ======== dsp_clk_init ========
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* Purpose:
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* Initialize CLK module.
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*/
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void dsp_clk_init(void)
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{
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static struct platform_device dspbridge_device;
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dspbridge_device.dev.bus = &platform_bus_type;
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iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
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if (IS_ERR(iva2_clk))
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dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
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ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
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ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
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ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
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if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
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dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
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ssi.sst_fck, ssi.ssr_fck, ssi.ick);
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}
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#ifdef CONFIG_OMAP_MCBSP
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static void mcbsp_clk_prepare(bool flag, u8 id)
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{
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struct cfg_hostres *resources;
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struct dev_object *hdev_object = NULL;
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struct bridge_dev_context *bridge_context = NULL;
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u32 val;
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hdev_object = (struct dev_object *)drv_get_first_dev_object();
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if (!hdev_object)
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return;
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dev_get_bridge_context(hdev_object, &bridge_context);
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if (!bridge_context)
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return;
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resources = bridge_context->resources;
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if (!resources)
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return;
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if (flag) {
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if (id == DSP_CLK_MCBSP1) {
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/* set MCBSP1_CLKS, on McBSP1 ON */
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val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
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val |= 1 << 2;
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__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
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} else if (id == DSP_CLK_MCBSP2) {
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/* set MCBSP2_CLKS, on McBSP2 ON */
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val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
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val |= 1 << 6;
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__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
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}
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} else {
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if (id == DSP_CLK_MCBSP1) {
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/* clear MCBSP1_CLKS, on McBSP1 OFF */
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val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
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val &= ~(1 << 2);
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__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
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} else if (id == DSP_CLK_MCBSP2) {
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/* clear MCBSP2_CLKS, on McBSP2 OFF */
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val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
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val &= ~(1 << 6);
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__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
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}
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}
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}
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#endif
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/**
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* dsp_gpt_wait_overflow - set gpt overflow and wait for fixed timeout
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* @clk_id: GP Timer clock id.
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* @load: Overflow value.
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*
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* Sets an overflow interrupt for the desired GPT waiting for a timeout
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* of 5 msecs for the interrupt to occur.
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*/
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void dsp_gpt_wait_overflow(short int clk_id, unsigned int load)
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{
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struct omap_dm_timer *gpt = timer[clk_id - 1];
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unsigned long timeout;
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if (!gpt)
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return;
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/* Enable overflow interrupt */
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omap_dm_timer_set_int_enable(gpt, OMAP_TIMER_INT_OVERFLOW);
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/*
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* Set counter value to overflow counter after
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* one tick and start timer.
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*/
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omap_dm_timer_set_load_start(gpt, 0, load);
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/* Wait 80us for timer to overflow */
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udelay(80);
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timeout = msecs_to_jiffies(5);
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/* Check interrupt status and wait for interrupt */
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while (!(omap_dm_timer_read_status(gpt) & OMAP_TIMER_INT_OVERFLOW)) {
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if (time_is_after_jiffies(timeout)) {
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pr_err("%s: GPTimer interrupt failed\n", __func__);
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break;
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}
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}
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}
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/*
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* ======== dsp_clk_enable ========
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* Purpose:
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* Enable Clock .
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*
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*/
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int dsp_clk_enable(enum dsp_clk_id clk_id)
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{
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int status = 0;
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if (is_dsp_clk_active(dsp_clocks, clk_id)) {
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dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
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goto out;
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}
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switch (get_clk_type(clk_id)) {
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case IVA2_CLK:
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clk_enable(iva2_clk);
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break;
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case GPT_CLK:
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timer[clk_id - 1] =
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omap_dm_timer_request_specific(DMT_ID(clk_id));
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break;
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#ifdef CONFIG_OMAP_MCBSP
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case MCBSP_CLK:
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mcbsp_clk_prepare(true, clk_id);
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omap_mcbsp_set_io_type(MCBSP_ID(clk_id), OMAP_MCBSP_POLL_IO);
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omap_mcbsp_request(MCBSP_ID(clk_id));
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break;
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#endif
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case WDT_CLK:
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dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
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break;
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case SSI_CLK:
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clk_enable(ssi.sst_fck);
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clk_enable(ssi.ssr_fck);
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clk_enable(ssi.ick);
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/*
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* The SSI module need to configured not to have the Forced
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* idle for master interface. If it is set to forced idle,
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* the SSI module is transitioning to standby thereby causing
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* the client in the DSP hang waiting for the SSI module to
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* be active after enabling the clocks
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*/
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ssi_clk_prepare(true);
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break;
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default:
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dev_err(bridge, "Invalid clock id for enable\n");
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status = -EPERM;
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}
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if (!status)
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set_dsp_clk_active(&dsp_clocks, clk_id);
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out:
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return status;
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}
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/**
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* dsp_clock_enable_all - Enable clocks used by the DSP
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* @dev_context Driver's device context strucure
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*
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* This function enables all the peripheral clocks that were requested by DSP.
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*/
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u32 dsp_clock_enable_all(u32 dsp_per_clocks)
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{
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u32 clk_id;
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u32 status = -EPERM;
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for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
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if (is_dsp_clk_active(dsp_per_clocks, clk_id))
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status = dsp_clk_enable(clk_id);
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}
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return status;
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}
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/*
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* ======== dsp_clk_disable ========
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* Purpose:
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* Disable the clock.
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*
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*/
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int dsp_clk_disable(enum dsp_clk_id clk_id)
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{
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int status = 0;
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if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
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dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
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goto out;
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}
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switch (get_clk_type(clk_id)) {
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case IVA2_CLK:
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clk_disable(iva2_clk);
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break;
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case GPT_CLK:
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omap_dm_timer_free(timer[clk_id - 1]);
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break;
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#ifdef CONFIG_OMAP_MCBSP
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case MCBSP_CLK:
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mcbsp_clk_prepare(false, clk_id);
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omap_mcbsp_free(MCBSP_ID(clk_id));
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break;
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#endif
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case WDT_CLK:
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dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
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break;
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case SSI_CLK:
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ssi_clk_prepare(false);
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ssi_clk_prepare(false);
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clk_disable(ssi.sst_fck);
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clk_disable(ssi.ssr_fck);
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clk_disable(ssi.ick);
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break;
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default:
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dev_err(bridge, "Invalid clock id for disable\n");
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status = -EPERM;
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}
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if (!status)
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set_dsp_clk_inactive(&dsp_clocks, clk_id);
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out:
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return status;
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}
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/**
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* dsp_clock_disable_all - Disable all active clocks
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* @dev_context Driver's device context structure
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*
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* This function disables all the peripheral clocks that were enabled by DSP.
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* It is meant to be called only when DSP is entering hibernation or when DSP
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* is in error state.
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*/
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u32 dsp_clock_disable_all(u32 dsp_per_clocks)
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{
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u32 clk_id;
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u32 status = -EPERM;
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for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
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if (is_dsp_clk_active(dsp_per_clocks, clk_id))
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status = dsp_clk_disable(clk_id);
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}
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return status;
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}
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u32 dsp_clk_get_iva2_rate(void)
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{
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u32 clk_speed_khz;
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clk_speed_khz = clk_get_rate(iva2_clk);
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clk_speed_khz /= 1000;
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dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
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return clk_speed_khz;
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}
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void ssi_clk_prepare(bool FLAG)
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{
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void __iomem *ssi_base;
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unsigned int value;
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ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
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if (!ssi_base) {
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pr_err("%s: error, SSI not configured\n", __func__);
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return;
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}
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if (FLAG) {
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/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
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* no idle
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*/
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value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
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} else {
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/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
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* forced idle
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*/
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value = SSI_AUTOIDLE;
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}
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__raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
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iounmap(ssi_base);
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}
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