479 lines
9.6 KiB
C
479 lines
9.6 KiB
C
/******************************************************************************
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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******************************************************************************/
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#ifndef _RTL819XU_HTTYPE_H_
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#define _RTL819XU_HTTYPE_H_
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#define HT_OPMODE_NO_PROTECT 0
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#define HT_OPMODE_OPTIONAL 1
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#define HT_OPMODE_40MHZ_PROTECT 2
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#define HT_OPMODE_MIXED 3
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#define MIMO_PS_STATIC 0
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#define MIMO_PS_DYNAMIC 1
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#define MIMO_PS_NOLIMIT 3
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#define sHTCLng 4
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#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
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#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
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#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
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typedef enum _HT_MCS_RATE{
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HT_MCS0 = 0x00000001,
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HT_MCS1 = 0x00000002,
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HT_MCS2 = 0x00000004,
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HT_MCS3 = 0x00000008,
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HT_MCS4 = 0x00000010,
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HT_MCS5 = 0x00000020,
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HT_MCS6 = 0x00000040,
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HT_MCS7 = 0x00000080,
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HT_MCS8 = 0x00000100,
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HT_MCS9 = 0x00000200,
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HT_MCS10 = 0x00000400,
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HT_MCS11 = 0x00000800,
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HT_MCS12 = 0x00001000,
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HT_MCS13 = 0x00002000,
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HT_MCS14 = 0x00004000,
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HT_MCS15 = 0x00008000,
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}HT_MCS_RATE,*PHT_MCS_RATE;
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typedef enum _HT_CHANNEL_WIDTH{
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HT_CHANNEL_WIDTH_20 = 0,
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HT_CHANNEL_WIDTH_20_40 = 1,
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}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
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typedef enum _HT_EXTCHNL_OFFSET{
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HT_EXTCHNL_OFFSET_NO_EXT = 0,
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HT_EXTCHNL_OFFSET_UPPER = 1,
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HT_EXTCHNL_OFFSET_NO_DEF = 2,
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HT_EXTCHNL_OFFSET_LOWER = 3,
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}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
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typedef enum _CHNLOP{
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CHNLOP_NONE = 0,
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CHNLOP_SCAN = 1,
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CHNLOP_SWBW = 2,
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CHNLOP_SWCHNL = 3,
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} CHNLOP, *PCHNLOP;
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#define CHHLOP_IN_PROGRESS(_pHTInfo) \
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((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false
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/*
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typedef union _HT_CAPABILITY{
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u16 ShortData;
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u8 CharData[2];
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struct
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{
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u16 AdvCoding:1;
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u16 ChlWidth:1;
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u16 MimoPwrSave:2;
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u16 GreenField:1;
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u16 ShortGI20Mhz:1;
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u16 ShortGI40Mhz:1;
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u16 STBC:1;
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u16 BeamForm:1;
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u16 DelayBA:1;
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u16 MaxAMSDUSize:1;
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u16 DssCCk:1;
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u16 PSMP:1;
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u16 Rsvd:3;
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}Field;
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}HT_CAPABILITY, *PHT_CAPABILITY;
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typedef union _HT_CAPABILITY_MACPARA{
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u8 ShortData;
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u8 CharData[1];
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struct
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{
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u8 MaxRxAMPDU:2;
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u8 MPDUDensity:2;
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u8 Rsvd:4;
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}Field;
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}HT_CAPABILITY_MACPARA, *PHT_CAPABILITY_MACPARA;
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*/
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typedef enum _HT_ACTION{
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ACT_RECOMMAND_WIDTH = 0,
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ACT_MIMO_PWR_SAVE = 1,
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ACT_PSMP = 2,
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ACT_SET_PCO_PHASE = 3,
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ACT_MIMO_CHL_MEASURE = 4,
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ACT_RECIPROCITY_CORRECT = 5,
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ACT_MIMO_CSI_MATRICS = 6,
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ACT_MIMO_NOCOMPR_STEER = 7,
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ACT_MIMO_COMPR_STEER = 8,
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ACT_ANTENNA_SELECT = 9,
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} HT_ACTION, *PHT_ACTION;
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typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
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SC_MODE_DUPLICATE = 0,
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SC_MODE_LOWER = 1,
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SC_MODE_UPPER = 2,
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SC_MODE_FULL40MHZ = 3,
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}HT_BW40_SC_E;
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struct ht_capab_ele {
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u8 AdvCoding:1;
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u8 ChlWidth:1;
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u8 MimoPwrSave:2;
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u8 GreenField:1;
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u8 ShortGI20Mhz:1;
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u8 ShortGI40Mhz:1;
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u8 TxSTBC:1;
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u8 RxSTBC:2;
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u8 DelayBA:1;
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u8 MaxAMSDUSize:1;
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u8 DssCCk:1;
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u8 PSMP:1;
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u8 Rsvd1:1;
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u8 LSigTxopProtect:1;
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u8 MaxRxAMPDUFactor:2;
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u8 MPDUDensity:3;
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u8 Rsvd2:3;
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u8 MCS[16];
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u16 ExtHTCapInfo;
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u8 TxBFCap[4];
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u8 ASCap;
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} __packed;
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struct ht_info_ele {
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u8 ControlChl;
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u8 ExtChlOffset:2;
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u8 RecommemdedTxWidth:1;
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u8 RIFS:1;
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u8 PSMPAccessOnly:1;
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u8 SrvIntGranularity:3;
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u8 OptMode:2;
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u8 NonGFDevPresent:1;
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u8 Revd1:5;
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u8 Revd2:8;
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u8 Rsvd3:6;
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u8 DualBeacon:1;
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u8 DualCTSProtect:1;
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u8 SecondaryBeacon:1;
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u8 LSigTxopProtectFull:1;
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u8 PcoActive:1;
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u8 PcoPhase:1;
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u8 Rsvd4:4;
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u8 BasicMSC[16];
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} __packed;
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struct mimops_ctrl {
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u8 MimoPsEnable:1;
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u8 MimoPsMode:1;
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u8 Reserved:6;
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};
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typedef enum _HT_SPEC_VER{
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HT_SPEC_VER_IEEE = 0,
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HT_SPEC_VER_EWC = 1,
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}HT_SPEC_VER, *PHT_SPEC_VER;
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typedef enum _HT_AGGRE_MODE_E{
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HT_AGG_AUTO = 0,
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HT_AGG_FORCE_ENABLE = 1,
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HT_AGG_FORCE_DISABLE = 2,
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}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
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struct rt_hi_throughput {
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u8 bEnableHT;
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u8 bCurrentHTSupport;
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u8 bRegBW40MHz;
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u8 bCurBW40MHz;
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u8 bRegShortGI40MHz;
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u8 bCurShortGI40MHz;
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u8 bRegShortGI20MHz;
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u8 bCurShortGI20MHz;
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u8 bRegSuppCCK;
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u8 bCurSuppCCK;
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HT_SPEC_VER ePeerHTSpecVer;
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struct ht_capab_ele SelfHTCap;
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struct ht_info_ele SelfHTInfo;
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u8 PeerHTCapBuf[32];
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u8 PeerHTInfoBuf[32];
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u8 bAMSDU_Support;
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u16 nAMSDU_MaxSize;
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u8 bCurrent_AMSDU_Support;
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u16 nCurrent_AMSDU_MaxSize;
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u8 bAMPDUEnable;
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u8 bCurrentAMPDUEnable;
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u8 AMPDU_Factor;
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u8 CurrentAMPDUFactor;
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u8 MPDU_Density;
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u8 CurrentMPDUDensity;
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HT_AGGRE_MODE_E ForcedAMPDUMode;
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u8 ForcedAMPDUFactor;
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u8 ForcedMPDUDensity;
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HT_AGGRE_MODE_E ForcedAMSDUMode;
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u16 ForcedAMSDUMaxSize;
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u8 bForcedShortGI;
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u8 CurrentOpMode;
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u8 SelfMimoPs;
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u8 PeerMimoPs;
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HT_EXTCHNL_OFFSET CurSTAExtChnlOffset;
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u8 bCurTxBW40MHz;
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u8 PeerBandwidth;
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u8 bSwBwInProgress;
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CHNLOP ChnlOp;
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u8 SwBwStep;
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u8 bRegRT2RTAggregation;
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u8 RT2RT_HT_Mode;
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u8 bCurrentRT2RTAggregation;
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u8 bCurrentRT2RTLongSlotTime;
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u8 szRT2RTAggBuffer[10];
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u8 bRegRxReorderEnable;
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u8 bCurRxReorderEnable;
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u8 RxReorderWinSize;
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u8 RxReorderPendingTime;
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u16 RxReorderDropCounter;
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u8 bIsPeerBcm;
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u8 IOTPeer;
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u32 IOTAction;
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u8 IOTRaFunc;
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u8 bWAIotBroadcom;
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u8 WAIotTH;
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u8 bAcceptAddbaReq;
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} __packed;
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struct rt_htinfo_sta_entry {
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u8 bEnableHT;
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u8 bSupportCck;
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u16 AMSDU_MaxSize;
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u8 AMPDU_Factor;
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u8 MPDU_Density;
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u8 HTHighestOperaRate;
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u8 bBw40MHz;
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u8 bCurTxBW40MHz;
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u8 bCurShortGI20MHz;
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u8 bCurShortGI40MHz;
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u8 MimoPs;
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u8 McsRateSet[16];
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u8 bCurRxReorderEnable;
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u16 nAMSDU_MaxSize;
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};//, *struct rt_htinfo_sta_entry *;
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struct bss_ht {
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u8 bdSupportHT;
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u8 bdHTCapBuf[32];
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u16 bdHTCapLen;
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u8 bdHTInfoBuf[32];
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u16 bdHTInfoLen;
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HT_SPEC_VER bdHTSpecVer;
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HT_CHANNEL_WIDTH bdBandWidth;
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u8 bdRT2RTAggregation;
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u8 bdRT2RTLongSlotTime;
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u8 RT2RT_HT_Mode;
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u8 bdHT1R;
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};
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struct mimo_rssi {
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u32 EnableAntenna;
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u32 AntennaA;
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u32 AntennaB;
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u32 AntennaC;
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u32 AntennaD;
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u32 Average;
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};//, *struct mimo_rssi *;
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struct mimo_evm {
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u32 EVM1;
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u32 EVM2;
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};//, *struct mimo_evm *;
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struct false_alarm_stats {
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u32 Cnt_Parity_Fail;
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u32 Cnt_Rate_Illegal;
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u32 Cnt_Crc8_fail;
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u32 Cnt_Mcs_fail;
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u32 Cnt_Ofdm_fail;
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u32 Cnt_Cck_fail;
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u32 Cnt_all;
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};//, *struct false_alarm_stats *;
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extern u8 MCS_FILTER_ALL[16];
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extern u8 MCS_FILTER_1SS[16];
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#define PICK_RATE(_nLegacyRate, _nMcsRate) \
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(_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
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#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
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#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
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((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
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(LegacyRate):\
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(PICK_RATE(LegacyRate, HTRate))
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#define RATE_ADPT_1SS_MASK 0xFF
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#define RATE_ADPT_2SS_MASK 0xF0
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#define RATE_ADPT_MCS32_MASK 0x01
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#define IS_11N_MCS_RATE(rate) (rate&0x80)
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typedef enum _HT_AGGRE_SIZE{
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HT_AGG_SIZE_8K = 0,
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HT_AGG_SIZE_16K = 1,
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HT_AGG_SIZE_32K = 2,
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HT_AGG_SIZE_64K = 3,
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}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
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typedef enum _HT_IOT_PEER
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{
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HT_IOT_PEER_UNKNOWN = 0,
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HT_IOT_PEER_REALTEK = 1,
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HT_IOT_PEER_REALTEK_92SE = 2,
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HT_IOT_PEER_BROADCOM = 3,
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HT_IOT_PEER_RALINK = 4,
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HT_IOT_PEER_ATHEROS = 5,
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HT_IOT_PEER_CISCO= 6,
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HT_IOT_PEER_MARVELL=7,
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HT_IOT_PEER_92U_SOFTAP = 8,
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HT_IOT_PEER_SELF_SOFTAP = 9,
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HT_IOT_PEER_AIRGO = 10,
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HT_IOT_PEER_MAX = 11,
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}HT_IOT_PEER_E, *PHTIOT_PEER_E;
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typedef enum _HT_IOT_PEER_SUBTYPE
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{
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HT_IOT_PEER_ATHEROS_DIR635 = 0,
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}HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;
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typedef enum _HT_IOT_ACTION{
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HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
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HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
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HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
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HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
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HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
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HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
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HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
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HT_IOT_ACT_CDD_FSYNC = 0x00000080,
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HT_IOT_ACT_PURE_N_MODE = 0x00000100,
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HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
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HT_IOT_ACT_FORCED_RTS = 0x00000400,
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HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
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HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
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HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
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HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
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HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
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HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
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HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
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HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
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HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
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HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
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HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
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HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
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HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
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HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
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HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
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HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
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}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
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typedef enum _HT_IOT_RAFUNC{
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HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
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HT_IOT_RAFUNC_PEER_1R = 0x01,
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HT_IOT_RAFUNC_TX_AMSDU = 0x02,
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}HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
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typedef enum _RT_HT_CAP{
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RT_HT_CAP_USE_TURBO_AGGR = 0x01,
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RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
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RT_HT_CAP_USE_AMPDU = 0x04,
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RT_HT_CAP_USE_WOW = 0x8,
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RT_HT_CAP_USE_SOFTAP = 0x10,
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RT_HT_CAP_USE_92SE = 0x20,
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}RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;
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#endif
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