133 lines
5.0 KiB
C
133 lines
5.0 KiB
C
/******************************************************************************
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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******************************************************************************/
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#ifndef _R819XU_PHY_H
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#define _R819XU_PHY_H
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#define MAX_DOZE_WAITING_TIMES_9x 64
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
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#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
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#define RadioA_ArrayLength RadioA_ArrayLengthPciE
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#define RadioB_ArrayLength RadioB_ArrayLengthPciE
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#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
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#define RadioC_ArrayLength RadioC_ArrayLengthPciE
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#define RadioD_ArrayLength RadioD_ArrayLengthPciE
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#define PHY_REGArrayLength PHY_REGArrayLengthPciE
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#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
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#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
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#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
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#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
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#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
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#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
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#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
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#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
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typedef enum _SwChnlCmdID {
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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} SwChnlCmdID;
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/*--------------------------------Define structure--------------------------------*/
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typedef struct _SwChnlCmd {
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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} __attribute__ ((packed)) SwChnlCmd;
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extern u32 rtl819XMACPHY_Array_PG[];
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extern u32 rtl819XPHY_REG_1T2RArray[];
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extern u32 rtl819XAGCTAB_Array[];
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extern u32 rtl819XRadioA_Array[];
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extern u32 rtl819XRadioB_Array[];
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extern u32 rtl819XRadioC_Array[];
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extern u32 rtl819XRadioD_Array[];
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typedef enum _HW90_BLOCK {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4,
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} HW90_BLOCK_E, *PHW90_BLOCK_E;
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typedef enum _RF90_RADIO_PATH{
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RF90_PATH_A = 0,
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RF90_PATH_B = 1,
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RF90_PATH_C = 2,
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RF90_PATH_D = 3,
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RF90_PATH_MAX
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}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskByte3 0xff000000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
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extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
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extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
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extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
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extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
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extern void rtl8192_phy_configmac(struct net_device* dev);
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extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
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extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
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extern bool rtl8192_BBConfig(struct net_device* dev);
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extern void rtl8192_phy_getTxPower(struct net_device* dev);
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extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
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extern bool rtl8192_phy_RFConfig(struct net_device* dev);
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extern void rtl8192_phy_updateInitGain(struct net_device* dev);
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extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath);
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extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
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extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
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extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
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extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
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extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
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extern void PHY_SetRtl8192eRfOff(struct net_device *dev);
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bool
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SetRFPowerState(
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struct net_device* dev,
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RT_RF_POWER_STATE eRFPowerState
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);
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#define PHY_SetRFPowerState SetRFPowerState
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extern void PHY_ScanOperationBackup8192(struct net_device* dev,u8 Operation);
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#endif
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