936577c61d
Right now nobody cares, but the suspend/resume code will eventually want to suspend device interrupts without suspending the timer, and will depend on this flag to know. The modern x86 timer infrastructure uses the local APIC timers and never shows up as a device interrupt at all, so it isn't affected and doesn't need any of this. Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
137 lines
3.3 KiB
C
137 lines
3.3 KiB
C
/*
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* "High Precision Event Timer" based timekeeping.
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*
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* Copyright (c) 1991,1992,1995 Linus Torvalds
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* Copyright (c) 1994 Alan Modra
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* Copyright (c) 1995 Markus Kuhn
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* Copyright (c) 1996 Ingo Molnar
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* Copyright (c) 1998 Andrea Arcangeli
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* Copyright (c) 2002,2006 Vojtech Pavlik
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* Copyright (c) 2003 Andi Kleen
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* RTC support code taken from arch/i386/kernel/timers/time_hpet.c
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <linux/mca.h>
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#include <linux/nmi.h>
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#include <asm/i8253.h>
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#include <asm/hpet.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
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#include <asm/timer.h>
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volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
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unsigned long profile_pc(struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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/* Assume the lock function has either no stack frame or a copy
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of flags from PUSHF
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Eflags always has bits 22 and up cleared unlike kernel addresses. */
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if (!user_mode_vm(regs) && in_lock_functions(pc)) {
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#ifdef CONFIG_FRAME_POINTER
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return *(unsigned long *)(regs->bp + sizeof(long));
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#else
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unsigned long *sp = (unsigned long *)regs->sp;
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if (sp[0] >> 22)
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return sp[0];
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if (sp[1] >> 22)
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return sp[1];
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#endif
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}
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return pc;
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}
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EXPORT_SYMBOL(profile_pc);
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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inc_irq_stat(irq0_irqs);
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global_clock_event->event_handler(global_clock_event);
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#ifdef CONFIG_MCA
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if (MCA_bus) {
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u8 irq_v = inb_p(0x61); /* read the current state */
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outb_p(irq_v|0x80, 0x61); /* reset the IRQ */
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}
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#endif
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return IRQ_HANDLED;
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}
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/* calibrate_cpu is used on systems with fixed rate TSCs to determine
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* processor frequency */
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#define TICK_COUNT 100000000
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unsigned long __init calibrate_cpu(void)
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{
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int tsc_start, tsc_now;
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int i, no_ctr_free;
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unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
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unsigned long flags;
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for (i = 0; i < 4; i++)
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if (avail_to_resrv_perfctr_nmi_bit(i))
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break;
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no_ctr_free = (i == 4);
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if (no_ctr_free) {
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WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
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"cpu_khz value may be incorrect.\n");
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i = 3;
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rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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rdmsrl(MSR_K7_PERFCTR3, pmc3);
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} else {
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reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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local_irq_save(flags);
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/* start measuring cycles, incrementing from 0 */
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wrmsrl(MSR_K7_PERFCTR0 + i, 0);
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wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
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rdtscl(tsc_start);
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do {
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rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
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tsc_now = get_cycles();
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} while ((tsc_now - tsc_start) < TICK_COUNT);
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local_irq_restore(flags);
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if (no_ctr_free) {
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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wrmsrl(MSR_K7_PERFCTR3, pmc3);
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wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
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} else {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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return pmc_now * tsc_khz / (tsc_now - tsc_start);
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING | IRQF_TIMER,
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.mask = CPU_MASK_NONE,
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.name = "timer"
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};
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void __init hpet_time_init(void)
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{
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if (!hpet_enable())
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setup_pit_timer();
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irq0.mask = cpumask_of_cpu(0);
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setup_irq(0, &irq0);
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}
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void __init time_init(void)
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{
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tsc_init();
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late_time_init = choose_time_init();
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}
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