9fccc82e19
In PG2 only the last frame in the aggregate buffer should be aligned to the sdio block size. This frame's header msb should be set to 0, while in all the previous frames in the aggregation buffer, this bit should be set to 1. [Add a HW op for setting the frame ctrl bit only for 18xx. Other minor cleanups - Arik] [Make the pre_pkt_send operation optional -- Luca] Signed-off-by: Ido Reis <idor@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/*
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* This file is part of wl18xx
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*
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* Copyright (C) 2011 Texas Instruments. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL18XX_TX_H__
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#define __WL18XX_TX_H__
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#include "../wlcore/wlcore.h"
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#define WL18XX_TX_HW_BLOCK_SPARE 1
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/* for special cases - namely, TKIP and GEM */
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#define WL18XX_TX_HW_EXTRA_BLOCK_SPARE 2
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#define WL18XX_TX_HW_BLOCK_SIZE 268
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#define WL18XX_TX_STATUS_DESC_ID_MASK 0x7F
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#define WL18XX_TX_STATUS_STAT_BIT_IDX 7
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/* Indicates this TX HW frame is not padded to SDIO block size */
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#define WL18XX_TX_CTRL_NOT_PADDED BIT(7)
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/*
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* The FW uses a special bit to indicate a wide channel should be used in
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* the rate policy.
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*/
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#define CONF_TX_RATE_USE_WIDE_CHAN BIT(31)
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void wl18xx_tx_immediate_complete(struct wl1271 *wl);
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#endif /* __WL12XX_TX_H__ */
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