1aad54a99b
This moves in the necessary libgcc bits for SUPERH32 and drops the libgcc linking for the regular targets. This in turn allows us to rip out quite a few hacks both in sh_ksyms_32 and arch/sh/Makefile. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
193 lines
3.7 KiB
ArmAsm
193 lines
3.7 KiB
ArmAsm
/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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2004, 2005, 2006
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Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file into combinations with other programs,
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and to distribute those combinations without any restriction coming
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from the use of this file. (The General Public License restrictions
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do apply in other respects; for example, they cover modification of
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the file, and distribution when not linked into a combine
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executable.)
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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!! libgcc routines for the Renesas / SuperH SH CPUs.
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!! Contributed by Steve Chamberlain.
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!! sac@cygnus.com
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!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
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!! recoded in assembly by Toshiyasu Morita
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!! tm@netcom.com
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/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
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ELF local label prefixes by J"orn Rennecke
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amylaar@cygnus.com */
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!
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! __lshrsi3
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!
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! Entry:
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!
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! r4: Value to shift
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! r5: Shifts
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!
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! Exit:
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!
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! r0: Result
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!
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! Destroys:
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!
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! (none)
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!
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.global __lshrsi3
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.align 2
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__lshrsi3:
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mov #31,r0
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and r0,r5
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mova lshrsi3_table,r0
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mov.b @(r0,r5),r5
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#ifdef __sh1__
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add r5,r0
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jmp @r0
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#else
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braf r5
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#endif
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mov r4,r0
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.align 2
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lshrsi3_table:
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.byte lshrsi3_0-lshrsi3_table
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.byte lshrsi3_1-lshrsi3_table
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.byte lshrsi3_2-lshrsi3_table
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.byte lshrsi3_3-lshrsi3_table
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.byte lshrsi3_4-lshrsi3_table
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.byte lshrsi3_5-lshrsi3_table
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.byte lshrsi3_6-lshrsi3_table
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.byte lshrsi3_7-lshrsi3_table
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.byte lshrsi3_8-lshrsi3_table
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.byte lshrsi3_9-lshrsi3_table
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.byte lshrsi3_10-lshrsi3_table
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.byte lshrsi3_11-lshrsi3_table
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.byte lshrsi3_12-lshrsi3_table
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.byte lshrsi3_13-lshrsi3_table
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.byte lshrsi3_14-lshrsi3_table
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.byte lshrsi3_15-lshrsi3_table
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.byte lshrsi3_16-lshrsi3_table
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.byte lshrsi3_17-lshrsi3_table
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.byte lshrsi3_18-lshrsi3_table
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.byte lshrsi3_19-lshrsi3_table
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.byte lshrsi3_20-lshrsi3_table
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.byte lshrsi3_21-lshrsi3_table
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.byte lshrsi3_22-lshrsi3_table
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.byte lshrsi3_23-lshrsi3_table
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.byte lshrsi3_24-lshrsi3_table
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.byte lshrsi3_25-lshrsi3_table
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.byte lshrsi3_26-lshrsi3_table
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.byte lshrsi3_27-lshrsi3_table
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.byte lshrsi3_28-lshrsi3_table
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.byte lshrsi3_29-lshrsi3_table
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.byte lshrsi3_30-lshrsi3_table
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.byte lshrsi3_31-lshrsi3_table
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lshrsi3_6:
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shlr2 r0
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lshrsi3_4:
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shlr2 r0
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lshrsi3_2:
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rts
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shlr2 r0
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lshrsi3_7:
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shlr2 r0
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lshrsi3_5:
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shlr2 r0
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lshrsi3_3:
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shlr2 r0
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lshrsi3_1:
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rts
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shlr r0
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lshrsi3_14:
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shlr2 r0
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lshrsi3_12:
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shlr2 r0
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lshrsi3_10:
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shlr2 r0
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lshrsi3_8:
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rts
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shlr8 r0
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lshrsi3_15:
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shlr2 r0
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lshrsi3_13:
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shlr2 r0
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lshrsi3_11:
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shlr2 r0
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lshrsi3_9:
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shlr8 r0
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rts
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shlr r0
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lshrsi3_22:
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shlr2 r0
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lshrsi3_20:
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shlr2 r0
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lshrsi3_18:
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shlr2 r0
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lshrsi3_16:
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rts
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shlr16 r0
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lshrsi3_23:
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shlr2 r0
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lshrsi3_21:
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shlr2 r0
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lshrsi3_19:
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shlr2 r0
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lshrsi3_17:
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shlr16 r0
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rts
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shlr r0
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lshrsi3_30:
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shlr2 r0
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lshrsi3_28:
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shlr2 r0
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lshrsi3_26:
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shlr2 r0
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lshrsi3_24:
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shlr16 r0
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rts
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shlr8 r0
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lshrsi3_31:
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shlr2 r0
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lshrsi3_29:
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shlr2 r0
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lshrsi3_27:
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shlr2 r0
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lshrsi3_25:
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shlr16 r0
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shlr8 r0
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rts
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shlr r0
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lshrsi3_0:
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rts
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nop
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