cf169702ba
This patch adds the detection of the northbridges in the AMD family 0x11 processors. It also fixes the magic numbers there while changing this code. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
/*
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* Shared support code for AMD K8 northbridges and derivates.
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* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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*/
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#include <linux/gfp.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/k8.h>
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int num_k8_northbridges;
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EXPORT_SYMBOL(num_k8_northbridges);
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static u32 *flush_words;
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struct pci_device_id k8_nb_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
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{}
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};
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EXPORT_SYMBOL(k8_nb_ids);
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struct pci_dev **k8_northbridges;
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EXPORT_SYMBOL(k8_northbridges);
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static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(&k8_nb_ids[0], dev));
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return dev;
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}
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int cache_k8_northbridges(void)
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{
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int i;
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struct pci_dev *dev;
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if (num_k8_northbridges)
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return 0;
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dev = NULL;
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while ((dev = next_k8_northbridge(dev)) != NULL)
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num_k8_northbridges++;
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k8_northbridges = kmalloc((num_k8_northbridges + 1) * sizeof(void *),
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GFP_KERNEL);
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if (!k8_northbridges)
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return -ENOMEM;
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if (!num_k8_northbridges) {
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k8_northbridges[0] = NULL;
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return 0;
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}
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flush_words = kmalloc(num_k8_northbridges * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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kfree(k8_northbridges);
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return -ENOMEM;
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}
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dev = NULL;
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i = 0;
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while ((dev = next_k8_northbridge(dev)) != NULL) {
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k8_northbridges[i] = dev;
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pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
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}
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k8_northbridges[i] = NULL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cache_k8_northbridges);
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/* Ignores subdevice/subvendor but as far as I can figure out
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they're useless anyways */
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int __init early_is_k8_nb(u32 device)
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{
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struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = k8_nb_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return 1;
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return 0;
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}
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void k8_flush_garts(void)
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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but I'm not sure if the hardware won't lose flush requests
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when another is pending. This whole thing is so expensive anyways
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < num_k8_northbridges; i++) {
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pci_write_config_dword(k8_northbridges[i], 0x9c,
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flush_words[i]|1);
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flushed++;
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}
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for (i = 0; i < num_k8_northbridges; i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(k8_northbridges[i],
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0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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spin_unlock_irqrestore(&gart_lock, flags);
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if (!flushed)
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printk("nothing to flush?\n");
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}
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EXPORT_SYMBOL_GPL(k8_flush_garts);
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