96c5590058
The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
18 lines
413 B
C
18 lines
413 B
C
/* Changed from asm-m68k version, Lineo Inc. May 2001 */
|
|
|
|
#ifndef _ASM_BFIN_PCI_H
|
|
#define _ASM_BFIN_PCI_H
|
|
|
|
#include <asm/scatterlist.h>
|
|
#include <asm-generic/pci-dma-compat.h>
|
|
#include <asm-generic/pci.h>
|
|
|
|
#define PCIBIOS_MIN_IO 0x00001000
|
|
#define PCIBIOS_MIN_MEM 0x10000000
|
|
|
|
static inline void pcibios_penalize_isa_irq(int irq)
|
|
{
|
|
/* We don't do dynamic PCI IRQ allocation */
|
|
}
|
|
|
|
#endif /* _ASM_BFIN_PCI_H */
|