8a4134322b
DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be buffered to improve performance. It will be used by the replacement for ARM/ARV32 specific dma_alloc_writecombine() function. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
43 lines
1.6 KiB
Text
43 lines
1.6 KiB
Text
DMA attributes
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==============
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This document describes the semantics of the DMA attributes that are
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defined in linux/dma-attrs.h.
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DMA_ATTR_WRITE_BARRIER
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----------------------
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DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA
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to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
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all pending DMA writes to complete, and thus provides a mechanism to
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strictly order DMA from a device across all intervening busses and
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bridges. This barrier is not specific to a particular type of
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interconnect, it applies to the system as a whole, and so its
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implementation must account for the idiosyncracies of the system all
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the way from the DMA device to memory.
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As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
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useful, suppose that a device does a DMA write to indicate that data is
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ready and available in memory. The DMA of the "completion indication"
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could race with data DMA. Mapping the memory used for completion
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indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
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DMA_ATTR_WEAK_ORDERING
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----------------------
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DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
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may be weakly ordered, that is that reads and writes may pass each other.
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Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
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those that do not will simply ignore the attribute and exhibit default
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behavior.
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DMA_ATTR_WRITE_COMBINE
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----------------------
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DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
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buffered to improve performance.
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Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
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those that do not will simply ignore the attribute and exhibit default
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behavior.
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