20443598d9
We use io_apic_setup_irq_pin() in order to configure pin's interrupt number polarity and type. This is done on every irq_create_of_mapping() which happens for instance during pci enable calls. Level typed interrupts are masked by default, edge are unmasked. On the first ->xlate() call the level interrupt is configured and masked. The driver calls request_irq() and the line is unmasked. Lets assume the interrupt line is shared with another device and we call pci_enable_device() for this device. The ->xlate() configures the pin again and it is masked. request_irq() does not unmask the line because it _is_ already unmasked according to its internal state. So the interrupt will never be unmasked again. This patch is based on an earlier work by Torben Hohn and solves the problem by configuring the pin only once. Since all devices must agree on the same type and polarity there is no point in configuring the pin more than once. [ tglx: Split out the ce4100 part into a separate patch ] Cc: Torben Hohn <torbenh@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/%3C20110427143052.GA15211%40linutronix.de%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
216 lines
5.3 KiB
C
216 lines
5.3 KiB
C
#ifndef _ASM_X86_IO_APIC_H
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#define _ASM_X86_IO_APIC_H
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#include <linux/types.h>
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#include <asm/mpspec.h>
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#include <asm/apicdef.h>
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#include <asm/irq_vectors.h>
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/*
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* Intel IO-APIC support for SMP and UP systems.
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*
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* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
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*/
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/* I/O Unit Redirection Table */
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#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
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#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
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#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
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#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
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#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
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#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
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#define IO_APIC_REDIR_MASKED (1 << 16)
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/*
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* The structure of the IO-APIC:
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*/
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union IO_APIC_reg_00 {
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u32 raw;
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struct {
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u32 __reserved_2 : 14,
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LTS : 1,
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delivery_type : 1,
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__reserved_1 : 8,
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ID : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_01 {
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u32 raw;
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struct {
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u32 version : 8,
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__reserved_2 : 7,
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PRQ : 1,
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entries : 8,
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__reserved_1 : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_02 {
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u32 raw;
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struct {
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u32 __reserved_2 : 24,
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arbitration : 4,
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__reserved_1 : 4;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_03 {
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u32 raw;
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struct {
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u32 boot_DT : 1,
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__reserved_1 : 31;
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} __attribute__ ((packed)) bits;
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};
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struct IO_APIC_route_entry {
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__u32 vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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__u32 __reserved_3 : 24,
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dest : 8;
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} __attribute__ ((packed));
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struct IR_IO_APIC_route_entry {
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__u64 vector : 8,
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zero : 3,
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index2 : 1,
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1,
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mask : 1,
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reserved : 31,
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format : 1,
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index : 15;
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} __attribute__ ((packed));
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#define IOAPIC_AUTO -1
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#define IOAPIC_EDGE 0
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#define IOAPIC_LEVEL 1
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#ifdef CONFIG_X86_IO_APIC
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/*
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* # of IO-APICs and # of IRQ routing registers
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*/
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extern int nr_ioapics;
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extern int nr_ioapic_registers[MAX_IO_APICS];
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#define MP_MAX_IOAPIC_PIN 127
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/* I/O APIC entries */
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extern struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
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/* # of MP IRQ source entries */
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extern int mp_irq_entries;
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/* MP IRQ source entries */
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extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* non-0 if default (table-less) MP configuration */
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extern int mpc_default_type;
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/* Older SiS APIC requires we rewrite the index register */
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extern int sis_apic_bug;
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/* 1 if "noapic" boot option passed */
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extern int skip_ioapic_setup;
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/* 1 if "noapic" boot option passed */
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extern int noioapicquirk;
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/* -1 if "noapic" boot option passed */
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extern int noioapicreroute;
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/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
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extern int timer_through_8259;
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/*
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* If we use the IO-APIC for IRQ routing, disable automatic
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* assignment of PCI IRQ's.
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*/
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#define io_apic_assign_pci_irqs \
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(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
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struct io_apic_irq_attr;
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extern int io_apic_set_pci_routing(struct device *dev, int irq,
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struct io_apic_irq_attr *irq_attr);
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void setup_IO_APIC_irq_extra(u32 gsi);
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extern void ioapic_and_gsi_init(void);
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extern void ioapic_insert_resources(void);
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int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
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extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
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extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
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extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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extern int get_nr_irqs_gsi(void);
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extern void setup_ioapic_ids_from_mpc(void);
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extern void setup_ioapic_ids_from_mpc_nocheck(void);
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struct mp_ioapic_gsi{
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u32 gsi_base;
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u32 gsi_end;
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};
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extern struct mp_ioapic_gsi mp_gsi_routing[];
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extern u32 gsi_top;
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int mp_find_ioapic(u32 gsi);
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int mp_find_ioapic_pin(int ioapic, u32 gsi);
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void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
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extern void __init pre_init_apic_IRQ0(void);
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extern void mp_save_irq(struct mpc_intsrc *m);
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extern void disable_ioapic_support(void);
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#else /* !CONFIG_X86_IO_APIC */
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#define io_apic_assign_pci_irqs 0
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#define setup_ioapic_ids_from_mpc x86_init_noop
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static const int timer_through_8259 = 0;
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static inline void ioapic_and_gsi_init(void) { }
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static inline void ioapic_insert_resources(void) { }
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#define gsi_top (NR_IRQS_LEGACY)
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static inline int mp_find_ioapic(u32 gsi) { return 0; }
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struct io_apic_irq_attr;
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static inline int io_apic_set_pci_routing(struct device *dev, int irq,
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struct io_apic_irq_attr *irq_attr) { return 0; }
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static inline struct IO_APIC_route_entry **alloc_ioapic_entries(void)
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{
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return NULL;
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}
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static inline void free_ioapic_entries(struct IO_APIC_route_entry **ent) { }
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static inline int save_IO_APIC_setup(struct IO_APIC_route_entry **ent)
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{
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return -ENOMEM;
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}
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static inline void mask_IO_APIC_setup(struct IO_APIC_route_entry **ent) { }
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static inline int restore_IO_APIC_setup(struct IO_APIC_route_entry **ent)
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{
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return -ENOMEM;
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}
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static inline void mp_save_irq(struct mpc_intsrc *m) { };
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static inline void disable_ioapic_support(void) { }
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#endif
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#endif /* _ASM_X86_IO_APIC_H */
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