8d318a50b3
This is a straightforward driver for the ST-Ericsson DMA40 DMA controller found in U8500, implemented akin to the existing COH 901 318 driver. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidh Kasagar <srinidhi.kasagar@stericsson.com> Cc: STEricsson_nomadik_linux@list.st.com Cc: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
454 lines
12 KiB
C
454 lines
12 KiB
C
/*
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* driver/dma/ste_dma40_ll.c
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*
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* Copyright (C) ST-Ericsson 2007-2010
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* License terms: GNU General Public License (GPL) version 2
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* Author: Per Friden <per.friden@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#include <linux/kernel.h>
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#include <plat/ste_dma40.h>
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#include "ste_dma40_ll.h"
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/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
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void d40_log_cfg(struct stedma40_chan_cfg *cfg,
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u32 *lcsp1, u32 *lcsp3)
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{
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u32 l3 = 0; /* dst */
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u32 l1 = 0; /* src */
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/* src is mem? -> increase address pos */
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if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
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cfg->dir == STEDMA40_MEM_TO_MEM)
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l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
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/* dst is mem? -> increase address pos */
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if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
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cfg->dir == STEDMA40_MEM_TO_MEM)
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l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
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/* src is hw? -> master port 1 */
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if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
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cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
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l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
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/* dst is hw? -> master port 1 */
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if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
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cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
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l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
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l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
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l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
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l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
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l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
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l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
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l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
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l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
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l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
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l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
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*lcsp1 = l1;
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*lcsp3 = l3;
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}
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/* Sets up SRC and DST CFG register for both logical and physical channels */
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void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
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u32 *src_cfg, u32 *dst_cfg, bool is_log)
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{
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u32 src = 0;
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u32 dst = 0;
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if (!is_log) {
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/* Physical channel */
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if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
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(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
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/* Set master port to 1 */
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src |= 1 << D40_SREG_CFG_MST_POS;
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src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
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if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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src |= 1 << D40_SREG_CFG_PHY_TM_POS;
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else
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src |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
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(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
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/* Set master port to 1 */
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dst |= 1 << D40_SREG_CFG_MST_POS;
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dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
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if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
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else
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dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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/* Interrupt on end of transfer for destination */
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dst |= 1 << D40_SREG_CFG_TIM_POS;
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/* Generate interrupt on error */
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src |= 1 << D40_SREG_CFG_EIM_POS;
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dst |= 1 << D40_SREG_CFG_EIM_POS;
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/* PSIZE */
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if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
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src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
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src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
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dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
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dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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/* Element size */
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src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
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dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
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} else {
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/* Logical channel */
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dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
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src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
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}
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if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
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src |= 1 << D40_SREG_CFG_PRI_POS;
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dst |= 1 << D40_SREG_CFG_PRI_POS;
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}
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src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
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dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
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*src_cfg = src;
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*dst_cfg = dst;
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}
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int d40_phy_fill_lli(struct d40_phy_lli *lli,
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dma_addr_t data,
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u32 data_size,
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int psize,
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dma_addr_t next_lli,
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u32 reg_cfg,
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bool term_int,
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u32 data_width,
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bool is_device)
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{
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int num_elems;
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if (psize == STEDMA40_PSIZE_PHY_1)
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num_elems = 1;
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else
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num_elems = 2 << psize;
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/*
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* Size is 16bit. data_width is 8, 16, 32 or 64 bit
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* Block large than 64 KiB must be split.
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*/
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if (data_size > (0xffff << data_width))
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return -EINVAL;
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/* Must be aligned */
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if (!IS_ALIGNED(data, 0x1 << data_width))
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return -EINVAL;
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/* Transfer size can't be smaller than (num_elms * elem_size) */
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if (data_size < num_elems * (0x1 << data_width))
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return -EINVAL;
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/* The number of elements. IE now many chunks */
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lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
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/*
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* Distance to next element sized entry.
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* Usually the size of the element unless you want gaps.
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*/
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if (!is_device)
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lli->reg_elt |= (0x1 << data_width) <<
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D40_SREG_ELEM_PHY_EIDX_POS;
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/* Where the data is */
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lli->reg_ptr = data;
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lli->reg_cfg = reg_cfg;
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/* If this scatter list entry is the last one, no next link */
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if (next_lli == 0)
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lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
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else
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lli->reg_lnk = next_lli;
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/* Set/clear interrupt generation on this link item.*/
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if (term_int)
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lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
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else
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lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
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/* Post link */
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lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
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return 0;
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}
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int d40_phy_sg_to_lli(struct scatterlist *sg,
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int sg_len,
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dma_addr_t target,
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struct d40_phy_lli *lli,
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dma_addr_t lli_phys,
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u32 reg_cfg,
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u32 data_width,
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int psize,
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bool term_int)
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{
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int total_size = 0;
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int i;
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struct scatterlist *current_sg = sg;
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dma_addr_t next_lli_phys;
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dma_addr_t dst;
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int err = 0;
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for_each_sg(sg, current_sg, sg_len, i) {
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total_size += sg_dma_len(current_sg);
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/* If this scatter list entry is the last one, no next link */
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if (sg_len - 1 == i)
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next_lli_phys = 0;
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else
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next_lli_phys = ALIGN(lli_phys + (i + 1) *
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sizeof(struct d40_phy_lli),
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D40_LLI_ALIGN);
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if (target)
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dst = target;
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else
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dst = sg_phys(current_sg);
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err = d40_phy_fill_lli(&lli[i],
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dst,
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sg_dma_len(current_sg),
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psize,
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next_lli_phys,
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reg_cfg,
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!next_lli_phys,
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data_width,
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target == dst);
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if (err)
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goto err;
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}
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return total_size;
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err:
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return err;
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}
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void d40_phy_lli_write(void __iomem *virtbase,
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u32 phy_chan_num,
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struct d40_phy_lli *lli_dst,
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struct d40_phy_lli *lli_src)
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{
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writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
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writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
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writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
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writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
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writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
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writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
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writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
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writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
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phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
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}
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/* DMA logical lli operations */
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void d40_log_fill_lli(struct d40_log_lli *lli,
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dma_addr_t data, u32 data_size,
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u32 lli_next_off, u32 reg_cfg,
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u32 data_width,
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bool term_int, bool addr_inc)
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{
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lli->lcsp13 = reg_cfg;
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/* The number of elements to transfer */
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lli->lcsp02 = ((data_size >> data_width) <<
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D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
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/* 16 LSBs address of the current element */
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lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
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/* 16 MSBs address of the current element */
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lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
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if (addr_inc)
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lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
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lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
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/* If this scatter list entry is the last one, no next link */
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lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
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D40_MEM_LCSP1_SLOS_MASK;
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if (term_int)
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lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
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else
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lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
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}
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int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
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struct scatterlist *sg,
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int sg_len,
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struct d40_log_lli_bidir *lli,
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struct d40_def_lcsp *lcsp,
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u32 src_data_width,
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u32 dst_data_width,
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enum dma_data_direction direction,
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bool term_int, dma_addr_t dev_addr, int max_len,
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int llis_per_log)
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{
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int total_size = 0;
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struct scatterlist *current_sg = sg;
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int i;
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u32 next_lli_off_dst;
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u32 next_lli_off_src;
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next_lli_off_src = 0;
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next_lli_off_dst = 0;
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for_each_sg(sg, current_sg, sg_len, i) {
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total_size += sg_dma_len(current_sg);
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/*
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* If this scatter list entry is the last one or
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* max length, terminate link.
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*/
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if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
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next_lli_off_src = 0;
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next_lli_off_dst = 0;
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} else {
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if (next_lli_off_dst == 0 &&
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next_lli_off_src == 0) {
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/* The first lli will be at next_lli_off */
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next_lli_off_dst = (lcla->dst_id *
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llis_per_log + 1);
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next_lli_off_src = (lcla->src_id *
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llis_per_log + 1);
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} else {
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next_lli_off_dst++;
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next_lli_off_src++;
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}
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}
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if (direction == DMA_TO_DEVICE) {
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d40_log_fill_lli(&lli->src[i],
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sg_phys(current_sg),
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sg_dma_len(current_sg),
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next_lli_off_src,
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lcsp->lcsp1, src_data_width,
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term_int && !next_lli_off_src,
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true);
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d40_log_fill_lli(&lli->dst[i],
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dev_addr,
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sg_dma_len(current_sg),
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next_lli_off_dst,
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lcsp->lcsp3, dst_data_width,
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/* No next == terminal interrupt */
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term_int && !next_lli_off_dst,
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false);
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} else {
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d40_log_fill_lli(&lli->dst[i],
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sg_phys(current_sg),
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sg_dma_len(current_sg),
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next_lli_off_dst,
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lcsp->lcsp3, dst_data_width,
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/* No next == terminal interrupt */
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term_int && !next_lli_off_dst,
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true);
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d40_log_fill_lli(&lli->src[i],
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dev_addr,
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sg_dma_len(current_sg),
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next_lli_off_src,
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lcsp->lcsp1, src_data_width,
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term_int && !next_lli_off_src,
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false);
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}
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}
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return total_size;
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}
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int d40_log_sg_to_lli(int lcla_id,
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struct scatterlist *sg,
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int sg_len,
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struct d40_log_lli *lli_sg,
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u32 lcsp13, /* src or dst*/
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u32 data_width,
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bool term_int, int max_len, int llis_per_log)
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{
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int total_size = 0;
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struct scatterlist *current_sg = sg;
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int i;
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u32 next_lli_off = 0;
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for_each_sg(sg, current_sg, sg_len, i) {
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total_size += sg_dma_len(current_sg);
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/*
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* If this scatter list entry is the last one or
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* max length, terminate link.
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*/
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if (sg_len - 1 == i || ((i+1) % max_len == 0))
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next_lli_off = 0;
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else {
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if (next_lli_off == 0)
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/* The first lli will be at next_lli_off */
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next_lli_off = lcla_id * llis_per_log + 1;
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else
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next_lli_off++;
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}
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d40_log_fill_lli(&lli_sg[i],
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sg_phys(current_sg),
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sg_dma_len(current_sg),
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next_lli_off,
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lcsp13, data_width,
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term_int && !next_lli_off,
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true);
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}
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return total_size;
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}
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void d40_log_lli_write(struct d40_log_lli_full *lcpa,
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struct d40_log_lli *lcla_src,
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struct d40_log_lli *lcla_dst,
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struct d40_log_lli *lli_dst,
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struct d40_log_lli *lli_src,
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int llis_per_log)
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{
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u32 slos = 0;
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u32 dlos = 0;
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int i;
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lcpa->lcsp0 = lli_src->lcsp02;
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lcpa->lcsp1 = lli_src->lcsp13;
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lcpa->lcsp2 = lli_dst->lcsp02;
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lcpa->lcsp3 = lli_dst->lcsp13;
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slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
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dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
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for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
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writel(lli_src[i+1].lcsp02, &lcla_src[i].lcsp02);
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writel(lli_src[i+1].lcsp13, &lcla_src[i].lcsp13);
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writel(lli_dst[i+1].lcsp02, &lcla_dst[i].lcsp02);
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writel(lli_dst[i+1].lcsp13, &lcla_dst[i].lcsp13);
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slos = lli_src[i+1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
|
|
dlos = lli_dst[i+1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
|
|
}
|
|
}
|