495 lines
12 KiB
C
495 lines
12 KiB
C
#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/workqueue.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/sysfs.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include "../iio.h"
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#include "../sysfs.h"
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#include "../ring_sw.h"
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#include "../kfifo_buf.h"
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#include "accel.h"
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#include "../trigger.h"
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#include "lis3l02dq.h"
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/**
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* combine_8_to_16() utility function to munge to u8s into u16
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**/
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static inline u16 combine_8_to_16(u8 lower, u8 upper)
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{
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u16 _lower = lower;
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u16 _upper = upper;
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return _lower | (_upper << 8);
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}
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/**
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* lis3l02dq_poll_func_th() top half interrupt handler called by trigger
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* @private_data: iio_dev
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**/
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static void lis3l02dq_poll_func_th(struct iio_dev *indio_dev, s64 time)
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{
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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/* in this case we need to slightly extend the helper function */
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iio_sw_poll_func_th(indio_dev, time);
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/* Indicate that this interrupt is being handled */
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/* Technically this is trigger related, but without this
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* handler running there is currently now way for the interrupt
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* to clear.
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*/
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st->inter = 1;
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}
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/**
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* lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
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**/
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static irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
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{
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disable_irq_nosync(irq);
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iio_trigger_poll(private, iio_get_time_ns());
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return IRQ_HANDLED;
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}
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/**
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* lis3l02dq_read_accel_from_ring() individual acceleration read from ring
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**/
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ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
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int index,
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int *val)
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{
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int ret;
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s16 *data;
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if (!iio_scan_mask_query(ring, index))
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return -EINVAL;
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data = kmalloc(ring->access.get_bytes_per_datum(ring),
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GFP_KERNEL);
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if (data == NULL)
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return -ENOMEM;
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ret = ring->access.read_last(ring, (u8 *)data);
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if (ret)
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goto error_free_data;
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*val = data[iio_scan_mask_count_to_right(ring, index)];
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error_free_data:
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kfree(data);
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return ret;
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}
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static const u8 read_all_tx_array[] = {
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
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LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
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};
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/**
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* lis3l02dq_read_all() Reads all channels currently selected
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* @st: device specific state
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* @rx_array: (dma capable) receive array, must be at least
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* 4*number of channels
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**/
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static int lis3l02dq_read_all(struct lis3l02dq_state *st, u8 *rx_array)
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{
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struct iio_ring_buffer *ring = st->help.indio_dev->ring;
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struct spi_transfer *xfers;
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struct spi_message msg;
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int ret, i, j = 0;
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xfers = kzalloc((ring->scan_count) * 2
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* sizeof(*xfers), GFP_KERNEL);
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if (!xfers)
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return -ENOMEM;
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mutex_lock(&st->buf_lock);
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for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
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if (ring->scan_mask & (1 << i)) {
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/* lower byte */
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xfers[j].tx_buf = st->tx + 2*j;
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st->tx[2*j] = read_all_tx_array[i*4];
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st->tx[2*j + 1] = 0;
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if (rx_array)
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xfers[j].rx_buf = rx_array + j*2;
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xfers[j].bits_per_word = 8;
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xfers[j].len = 2;
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xfers[j].cs_change = 1;
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j++;
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/* upper byte */
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xfers[j].tx_buf = st->tx + 2*j;
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st->tx[2*j] = read_all_tx_array[i*4 + 2];
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st->tx[2*j + 1] = 0;
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if (rx_array)
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xfers[j].rx_buf = rx_array + j*2;
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xfers[j].bits_per_word = 8;
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xfers[j].len = 2;
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xfers[j].cs_change = 1;
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j++;
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}
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/* After these are transmitted, the rx_buff should have
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* values in alternate bytes
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*/
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spi_message_init(&msg);
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for (j = 0; j < ring->scan_count * 2; j++)
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spi_message_add_tail(&xfers[j], &msg);
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ret = spi_sync(st->us, &msg);
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mutex_unlock(&st->buf_lock);
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kfree(xfers);
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return ret;
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}
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static void lis3l02dq_trigger_bh_to_ring(struct work_struct *work_s)
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{
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struct iio_sw_ring_helper_state *h
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= container_of(work_s, struct iio_sw_ring_helper_state,
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work_trigger_to_ring);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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st->inter = 0;
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iio_sw_trigger_bh_to_ring(work_s);
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}
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static int lis3l02dq_get_ring_element(struct iio_sw_ring_helper_state *h,
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u8 *buf)
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{
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int ret, i;
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u8 *rx_array ;
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s16 *data = (s16 *)buf;
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rx_array = kzalloc(4 * (h->indio_dev->ring->scan_count), GFP_KERNEL);
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if (rx_array == NULL)
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return -ENOMEM;
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ret = lis3l02dq_read_all(lis3l02dq_h_to_s(h), rx_array);
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if (ret < 0)
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return ret;
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for (i = 0; i < h->indio_dev->ring->scan_count; i++)
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data[i] = combine_8_to_16(rx_array[i*4+1],
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rx_array[i*4+3]);
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kfree(rx_array);
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return i*sizeof(data[0]);
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}
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/* Caller responsible for locking as necessary. */
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static int
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__lis3l02dq_write_data_ready_config(struct device *dev, bool state)
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{
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int ret;
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u8 valold;
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bool currentlyset;
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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/* Get the current event mask register */
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ret = lis3l02dq_spi_read_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&valold);
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if (ret)
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goto error_ret;
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/* Find out if data ready is already on */
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currentlyset
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= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
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/* Disable requested */
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if (!state && currentlyset) {
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/* disable the data ready signal */
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valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
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/* The double write is to overcome a hardware bug?*/
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&valold);
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if (ret)
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goto error_ret;
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&valold);
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if (ret)
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goto error_ret;
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free_irq(st->us->irq, st->trig);
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/* Enable requested */
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} else if (state && !currentlyset) {
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/* if not set, enable requested */
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/* first disable all events */
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ret = lis3l02dq_disable_all_events(indio_dev);
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if (ret < 0)
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goto error_ret;
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valold = ret |
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LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
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ret = request_irq(st->us->irq,
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lis3l02dq_data_rdy_trig_poll,
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IRQF_TRIGGER_RISING, "lis3l02dq_datardy",
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st->trig);
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if (ret)
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goto error_ret;
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&valold);
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if (ret) {
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free_irq(st->us->irq, st->trig);
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goto error_ret;
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}
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}
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return 0;
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error_ret:
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return ret;
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}
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/**
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* lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
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*
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* If disabling the interrupt also does a final read to ensure it is clear.
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* This is only important in some cases where the scan enable elements are
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* switched before the ring is reenabled.
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**/
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static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
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bool state)
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{
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struct lis3l02dq_state *st = trig->private_data;
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int ret = 0;
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u8 t;
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__lis3l02dq_write_data_ready_config(&st->help.indio_dev->dev, state);
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if (state == false) {
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/* possible quirk with handler currently worked around
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by ensuring the work queue is empty */
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flush_scheduled_work();
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/* Clear any outstanding ready events */
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ret = lis3l02dq_read_all(st, NULL);
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}
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lis3l02dq_spi_read_reg_8(st->help.indio_dev,
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LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
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&t);
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return ret;
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}
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static IIO_TRIGGER_NAME_ATTR;
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static struct attribute *lis3l02dq_trigger_attrs[] = {
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&dev_attr_name.attr,
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NULL,
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};
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static const struct attribute_group lis3l02dq_trigger_attr_group = {
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.attrs = lis3l02dq_trigger_attrs,
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};
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/**
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* lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
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* @trig: the datardy trigger
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*
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* As the trigger may occur on any data element being updated it is
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* really rather likely to occur during the read from the previous
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* trigger event. The only way to discover if this has occurred on
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* boards not supporting level interrupts is to take a look at the line.
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* If it is indicating another interrupt and we don't seem to have a
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* handler looking at it, then we need to notify the core that we need
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* to tell the triggering core to try reading all these again.
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**/
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static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
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{
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struct lis3l02dq_state *st = trig->private_data;
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enable_irq(st->us->irq);
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/* If gpio still high (or high again) */
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if (gpio_get_value(irq_to_gpio(st->us->irq)))
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if (st->inter == 0) {
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/* already interrupt handler dealing with it */
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disable_irq_nosync(st->us->irq);
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if (st->inter == 1) {
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/* interrupt handler snuck in between test
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* and disable */
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enable_irq(st->us->irq);
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return 0;
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}
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return -EAGAIN;
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}
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/* irq reenabled so success! */
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return 0;
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}
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int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
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{
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int ret;
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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st->trig = iio_allocate_trigger();
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if (!st->trig)
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return -ENOMEM;
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st->trig->name = kasprintf(GFP_KERNEL,
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"lis3l02dq-dev%d",
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indio_dev->id);
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if (!st->trig->name) {
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ret = -ENOMEM;
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goto error_free_trig;
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}
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st->trig->dev.parent = &st->us->dev;
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st->trig->owner = THIS_MODULE;
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st->trig->private_data = st;
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st->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state;
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st->trig->try_reenable = &lis3l02dq_trig_try_reen;
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st->trig->control_attrs = &lis3l02dq_trigger_attr_group;
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ret = iio_trigger_register(st->trig);
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if (ret)
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goto error_free_trig_name;
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return 0;
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error_free_trig_name:
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kfree(st->trig->name);
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error_free_trig:
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iio_free_trigger(st->trig);
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return ret;
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}
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void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
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{
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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iio_trigger_unregister(st->trig);
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kfree(st->trig->name);
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iio_free_trigger(st->trig);
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}
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void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
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{
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kfree(indio_dev->pollfunc);
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lis3l02dq_free_buf(indio_dev->ring);
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}
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static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
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{
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/* Disable unwanted channels otherwise the interrupt will not clear */
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u8 t;
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int ret;
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bool oneenabled = false;
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ret = lis3l02dq_spi_read_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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if (ret)
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goto error_ret;
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if (iio_scan_mask_query(indio_dev->ring, 0)) {
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t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
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oneenabled = true;
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} else
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t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
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if (iio_scan_mask_query(indio_dev->ring, 1)) {
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t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
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oneenabled = true;
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} else
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t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
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if (iio_scan_mask_query(indio_dev->ring, 2)) {
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t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
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oneenabled = true;
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} else
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t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
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if (!oneenabled) /* what happens in this case is unknown */
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return -EINVAL;
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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if (ret)
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goto error_ret;
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return iio_triggered_ring_postenable(indio_dev);
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error_ret:
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return ret;
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}
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/* Turn all channels on again */
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static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
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{
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u8 t;
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int ret;
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ret = iio_triggered_ring_predisable(indio_dev);
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if (ret)
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goto error_ret;
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ret = lis3l02dq_spi_read_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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if (ret)
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goto error_ret;
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t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
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LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
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LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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error_ret:
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return ret;
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}
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int lis3l02dq_configure_ring(struct iio_dev *indio_dev)
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{
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int ret;
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struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
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struct iio_ring_buffer *ring;
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INIT_WORK(&h->work_trigger_to_ring, lis3l02dq_trigger_bh_to_ring);
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h->get_ring_element = &lis3l02dq_get_ring_element;
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ring = lis3l02dq_alloc_buf(indio_dev);
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if (!ring)
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return -ENOMEM;
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indio_dev->ring = ring;
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/* Effectively select the ring buffer implementation */
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lis3l02dq_register_buf_funcs(&ring->access);
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ring->bpe = 2;
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ring->scan_timestamp = true;
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ring->preenable = &iio_sw_ring_preenable;
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ring->postenable = &lis3l02dq_ring_postenable;
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ring->predisable = &lis3l02dq_ring_predisable;
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ring->owner = THIS_MODULE;
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/* Set default scan mode */
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iio_scan_mask_set(ring, 0);
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iio_scan_mask_set(ring, 1);
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iio_scan_mask_set(ring, 2);
|
|
|
|
ret = iio_alloc_pollfunc(indio_dev, NULL, &lis3l02dq_poll_func_th);
|
|
if (ret)
|
|
goto error_iio_sw_rb_free;
|
|
indio_dev->modes |= INDIO_RING_TRIGGERED;
|
|
return 0;
|
|
|
|
error_iio_sw_rb_free:
|
|
lis3l02dq_free_buf(indio_dev->ring);
|
|
return ret;
|
|
}
|