2427bb241b
Instead of restoring registers blindly, restart the LCDC by going through the startup sequence when resuming from runtime PM suspend. All registers are now correctly initialized in the right order. As a side effect, this also gets rid fo a possible panning restore issue caused by always saving the frame buffer base address registers from set A instead of the currently active set. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
#ifndef SH_MOBILE_LCDCFB_H
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#define SH_MOBILE_LCDCFB_H
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#include <linux/completion.h>
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#include <linux/fb.h>
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#include <linux/mutex.h>
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#include <linux/wait.h>
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/* per-channel registers */
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enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
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LDSM2R, LDSA1R, LDSA2R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
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LDHAJR,
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NR_CH_REGS };
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#define PALETTE_NR 16
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struct sh_mobile_lcdc_priv;
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struct fb_info;
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struct backlight_device;
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/*
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* struct sh_mobile_lcdc_chan - LCDC display channel
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*
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* @base_addr_y: Frame buffer viewport base address (luma component)
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* @base_addr_c: Frame buffer viewport base address (chroma component)
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* @pitch: Frame buffer line pitch
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*/
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struct sh_mobile_lcdc_chan {
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struct sh_mobile_lcdc_priv *lcdc;
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unsigned long *reg_offs;
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unsigned long ldmt1r_value;
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unsigned long enabled; /* ME and SE in LDCNT2R */
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struct sh_mobile_lcdc_chan_cfg cfg;
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u32 pseudo_palette[PALETTE_NR];
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struct fb_info *info;
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struct backlight_device *bl;
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dma_addr_t dma_handle;
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struct fb_deferred_io defio;
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struct scatterlist *sglist;
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unsigned long frame_end;
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unsigned long pan_offset;
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wait_queue_head_t frame_end_wait;
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struct completion vsync_completion;
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struct fb_var_screeninfo display_var;
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int use_count;
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int blank_status;
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struct mutex open_lock; /* protects the use counter */
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int meram_enabled;
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unsigned long base_addr_y;
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unsigned long base_addr_c;
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unsigned int pitch;
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};
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#endif
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