1123 lines
30 KiB
C
1123 lines
30 KiB
C
/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/console.h>
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#include <plat/sram.h>
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#include <plat/clockdomain.h>
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#include <plat/powerdomain.h>
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#include <plat/serial.h>
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#include <plat/sdrc.h>
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#include <plat/prcm.h>
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#include <plat/gpmc.h>
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#include <plat/dma.h>
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#include <asm/tlbflush.h>
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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#include "prm.h"
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#include "pm.h"
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#include "sdrc.h"
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#include "control.h"
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#ifdef CONFIG_SUSPEND
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static suspend_state_t suspend_state = PM_SUSPEND_ON;
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static inline bool is_suspending(void)
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{
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return (suspend_state != PM_SUSPEND_ON);
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}
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#else
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static inline bool is_suspending(void)
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{
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return false;
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}
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#endif
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/* Scratchpad offsets */
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#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
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#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
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#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
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/* pm34xx errata defined in pm.h */
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u16 pm34xx_errata;
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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#ifdef CONFIG_SUSPEND
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u32 saved_state;
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#endif
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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static void (*_omap_sram_idle)(u32 *addr, int save_state);
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static int (*_omap_save_secure_sram)(u32 *addr);
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
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static struct powerdomain *core_pwrdm, *per_pwrdm;
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static struct powerdomain *cam_pwrdm;
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static inline void omap3_per_save_context(void)
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{
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omap_gpio_save_context();
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}
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static inline void omap3_per_restore_context(void)
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{
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omap_gpio_restore_context();
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}
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static void omap3_enable_io_chain(void)
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{
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int timeout = 0;
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if (omap_rev() >= OMAP3430_REV_ES3_1) {
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prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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/* Do a readback to assure write has been done */
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prm_read_mod_reg(WKUP_MOD, PM_WKEN);
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while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
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OMAP3430_ST_IO_CHAIN_MASK)) {
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timeout++;
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if (timeout > 1000) {
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printk(KERN_ERR "Wake up daisy chain "
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"activation failed.\n");
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return;
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}
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prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
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WKUP_MOD, PM_WKEN);
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}
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}
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}
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static void omap3_disable_io_chain(void)
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{
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if (omap_rev() >= OMAP3430_REV_ES3_1)
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prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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}
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static void omap3_core_save_context(void)
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{
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u32 control_padconf_off;
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/* Save the padconf registers */
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control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
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control_padconf_off |= START_PADCONF_SAVE;
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omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
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/* wait for the save to complete */
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while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
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& PADCONF_SAVE_DONE))
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udelay(1);
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/*
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* Force write last pad into memory, as this can fail in some
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* cases according to errata 1.157, 1.185
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*/
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omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
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OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
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/* Save the Interrupt controller context */
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omap_intc_save_context();
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/* Save the GPMC context */
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
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omap_dma_global_context_save();
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}
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static void omap3_core_restore_context(void)
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{
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/* Restore the control module context, padconf restored by h/w */
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omap3_control_restore_context();
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/* Restore the GPMC context */
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
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omap_dma_global_context_restore();
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}
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/*
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* FIXME: This function should be called before entering off-mode after
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* OMAP3 secure services have been accessed. Currently it is only called
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* once during boot sequence, but this works as we are not using secure
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* services.
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*/
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static void omap3_save_secure_ram_context(u32 target_mpu_state)
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{
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u32 ret;
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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/*
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* MPU next state must be set to POWER_ON temporarily,
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* otherwise the WFI executed inside the ROM code
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* will hang the system.
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*/
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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ret = _omap_save_secure_sram((u32 *)
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__pa(omap3_secure_ram_storage));
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pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
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/* Following is for error tracking, it should not happen */
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if (ret) {
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printk(KERN_ERR "save_secure_sram() returns %08x\n",
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ret);
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while (1)
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;
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}
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}
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}
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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static int prcm_clear_mod_irqs(s16 module, u8 regs)
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{
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u32 wkst, fclk, iclk, clken;
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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int c = 0;
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wkst = prm_read_mod_reg(module, wkst_off);
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wkst &= prm_read_mod_reg(module, grpsel_off);
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if (wkst) {
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iclk = cm_read_mod_reg(module, iclk_off);
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fclk = cm_read_mod_reg(module, fclk_off);
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while (wkst) {
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clken = wkst;
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cm_set_mod_reg_bits(clken, module, iclk_off);
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/*
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* For USBHOST, we don't know whether HOST1 or
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* HOST2 woke us up, so enable both f-clocks
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*/
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if (module == OMAP3430ES2_USBHOST_MOD)
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
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cm_set_mod_reg_bits(clken, module, fclk_off);
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prm_write_mod_reg(wkst, module, wkst_off);
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wkst = prm_read_mod_reg(module, wkst_off);
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c++;
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}
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cm_write_mod_reg(iclk, module, iclk_off);
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cm_write_mod_reg(fclk, module, fclk_off);
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}
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return c;
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}
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static int _prcm_int_handle_wakeup(void)
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{
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int c;
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c = prcm_clear_mod_irqs(WKUP_MOD, 1);
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c += prcm_clear_mod_irqs(CORE_MOD, 1);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
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}
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return c;
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}
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/*
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* PRCM Interrupt Handler
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*
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* The PRM_IRQSTATUS_MPU register indicates if there are any pending
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* interrupts from the PRCM for the MPU. These bits must be cleared in
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* order to clear the PRCM interrupt. The PRCM interrupt handler is
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* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
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* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
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* register indicates that a wake-up event is pending for the MPU and
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* this bit can only be cleared if the all the wake-up events latched
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* in the various PM_WKST_x registers have been cleared. The interrupt
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* handler is implemented using a do-while loop so that if a wake-up
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* event occurred during the processing of the prcm interrupt handler
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* (setting a bit in the corresponding PM_WKST_x register and thus
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* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
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* this would be handled.
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*/
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static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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{
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u32 irqenable_mpu, irqstatus_mpu;
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int c = 0;
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irqenable_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu &= irqenable_mpu;
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do {
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if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
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OMAP3430_IO_ST_MASK)) {
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c = _prcm_int_handle_wakeup();
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/*
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* Is the MPU PRCM interrupt handler racing with the
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* IVA2 PRCM interrupt handler ?
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*/
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WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
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"but no wakeup sources are marked\n");
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} else {
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/* XXX we need to expand our PRCM interrupt handler */
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WARN(1, "prcm: WARNING: PRCM interrupt received, but "
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"no code to handle it (%08x)\n", irqstatus_mpu);
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}
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prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu &= irqenable_mpu;
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} while (irqstatus_mpu);
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return IRQ_HANDLED;
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}
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static void restore_control_register(u32 val)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
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}
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/* Function to restore the table entry that was modified for enabling MMU */
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static void restore_table_entry(void)
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{
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void __iomem *scratchpad_address;
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u32 previous_value, control_reg_value;
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u32 *address;
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scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
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/* Get address of entry that was modified */
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address = (u32 *)__raw_readl(scratchpad_address +
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OMAP343X_TABLE_ADDRESS_OFFSET);
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/* Get the previous value which needs to be restored */
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previous_value = __raw_readl(scratchpad_address +
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OMAP343X_TABLE_VALUE_OFFSET);
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address = __va(address);
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*address = previous_value;
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flush_tlb_all();
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control_reg_value = __raw_readl(scratchpad_address
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+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
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/* This will enable caches and prediction */
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restore_control_register(control_reg_value);
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}
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void omap_sram_idle(void)
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{
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/* Variable to tell what needs to be saved and restored
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* in omap_sram_idle*/
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/* save_state = 0 => Nothing to save and restored */
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/* save_state = 1 => Only L1 and logic lost */
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/* save_state = 2 => Only L2 lost */
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/* save_state = 3 => L1, L2 and logic lost */
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int save_state = 0;
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int mpu_next_state = PWRDM_POWER_ON;
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int per_next_state = PWRDM_POWER_ON;
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int core_next_state = PWRDM_POWER_ON;
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int core_prev_state, per_prev_state;
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u32 sdrc_pwr = 0;
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if (!_omap_sram_idle)
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return;
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pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
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pwrdm_clear_all_prev_pwrst(neon_pwrdm);
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pwrdm_clear_all_prev_pwrst(core_pwrdm);
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pwrdm_clear_all_prev_pwrst(per_pwrdm);
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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switch (mpu_next_state) {
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case PWRDM_POWER_ON:
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case PWRDM_POWER_RET:
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/* No need to save context */
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save_state = 0;
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break;
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case PWRDM_POWER_OFF:
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save_state = 3;
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break;
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default:
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/* Invalid state */
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printk(KERN_ERR "Invalid mpu state in sram_idle\n");
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return;
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}
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pwrdm_pre_transition();
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/* NEON control */
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if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
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pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
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/* Enable IO-PAD and IO-CHAIN wakeups */
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per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
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core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
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if (omap3_has_io_wakeup() &&
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(per_next_state < PWRDM_POWER_ON ||
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core_next_state < PWRDM_POWER_ON)) {
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prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
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omap3_enable_io_chain();
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}
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/* Block console output in case it is on one of the OMAP UARTs */
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if (!is_suspending())
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if (per_next_state < PWRDM_POWER_ON ||
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core_next_state < PWRDM_POWER_ON)
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if (try_acquire_console_sem())
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goto console_still_active;
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/* PER */
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if (per_next_state < PWRDM_POWER_ON) {
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omap_uart_prepare_idle(2);
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omap_uart_prepare_idle(3);
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omap2_gpio_prepare_for_idle(per_next_state);
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if (per_next_state == PWRDM_POWER_OFF)
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omap3_per_save_context();
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}
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/* CORE */
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if (core_next_state < PWRDM_POWER_ON) {
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omap_uart_prepare_idle(0);
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omap_uart_prepare_idle(1);
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if (core_next_state == PWRDM_POWER_OFF) {
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omap3_core_save_context();
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omap3_prcm_save_context();
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}
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}
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omap3_intc_prepare_idle();
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/*
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* On EMU/HS devices ROM code restores a SRDC value
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* from scratchpad which has automatic self refresh on timeout
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* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
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* Hence store/restore the SDRC_POWER register here.
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*/
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if (omap_rev() >= OMAP3430_REV_ES3_0 &&
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omap_type() != OMAP2_DEVICE_TYPE_GP &&
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core_next_state == PWRDM_POWER_OFF)
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sdrc_pwr = sdrc_read_reg(SDRC_POWER);
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/*
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* omap3_arm_context is the location where ARM registers
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* get saved. The restore path then reads from this
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* location and restores them back.
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*/
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_omap_sram_idle(omap3_arm_context, save_state);
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cpu_init();
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/* Restore normal SDRC POWER settings */
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if (omap_rev() >= OMAP3430_REV_ES3_0 &&
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omap_type() != OMAP2_DEVICE_TYPE_GP &&
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core_next_state == PWRDM_POWER_OFF)
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sdrc_write_reg(sdrc_pwr, SDRC_POWER);
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/* Restore table entry modified during MMU restoration */
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if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
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restore_table_entry();
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/* CORE */
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if (core_next_state < PWRDM_POWER_ON) {
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core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
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if (core_prev_state == PWRDM_POWER_OFF) {
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omap3_core_restore_context();
|
|
omap3_prcm_restore_context();
|
|
omap3_sram_restore_context();
|
|
omap2_sms_restore_context();
|
|
}
|
|
omap_uart_resume_idle(0);
|
|
omap_uart_resume_idle(1);
|
|
if (core_next_state == PWRDM_POWER_OFF)
|
|
prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
|
OMAP3430_GR_MOD,
|
|
OMAP3_PRM_VOLTCTRL_OFFSET);
|
|
}
|
|
omap3_intc_resume_idle();
|
|
|
|
/* PER */
|
|
if (per_next_state < PWRDM_POWER_ON) {
|
|
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
|
|
omap2_gpio_resume_after_idle();
|
|
if (per_prev_state == PWRDM_POWER_OFF)
|
|
omap3_per_restore_context();
|
|
omap_uart_resume_idle(2);
|
|
omap_uart_resume_idle(3);
|
|
}
|
|
|
|
if (!is_suspending())
|
|
release_console_sem();
|
|
|
|
console_still_active:
|
|
/* Disable IO-PAD and IO-CHAIN wakeup */
|
|
if (omap3_has_io_wakeup() &&
|
|
(per_next_state < PWRDM_POWER_ON ||
|
|
core_next_state < PWRDM_POWER_ON)) {
|
|
prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
|
|
omap3_disable_io_chain();
|
|
}
|
|
|
|
pwrdm_post_transition();
|
|
|
|
omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
|
|
}
|
|
|
|
int omap3_can_sleep(void)
|
|
{
|
|
if (!sleep_while_idle)
|
|
return 0;
|
|
if (!omap_uart_can_sleep())
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
static void omap3_pm_idle(void)
|
|
{
|
|
local_irq_disable();
|
|
local_fiq_disable();
|
|
|
|
if (!omap3_can_sleep())
|
|
goto out;
|
|
|
|
if (omap_irq_pending() || need_resched())
|
|
goto out;
|
|
|
|
omap_sram_idle();
|
|
|
|
out:
|
|
local_fiq_enable();
|
|
local_irq_enable();
|
|
}
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
static int omap3_pm_suspend(void)
|
|
{
|
|
struct power_state *pwrst;
|
|
int state, ret = 0;
|
|
|
|
if (wakeup_timer_seconds || wakeup_timer_milliseconds)
|
|
omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
|
|
wakeup_timer_milliseconds);
|
|
|
|
/* Read current next_pwrsts */
|
|
list_for_each_entry(pwrst, &pwrst_list, node)
|
|
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
|
|
/* Set ones wanted by suspend */
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
|
goto restore;
|
|
if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
|
|
goto restore;
|
|
}
|
|
|
|
omap_uart_prepare_suspend();
|
|
omap3_intc_suspend();
|
|
|
|
omap_sram_idle();
|
|
|
|
restore:
|
|
/* Restore next_pwrsts */
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
|
|
if (state > pwrst->next_state) {
|
|
printk(KERN_INFO "Powerdomain (%s) didn't enter "
|
|
"target state %d\n",
|
|
pwrst->pwrdm->name, pwrst->next_state);
|
|
ret = -1;
|
|
}
|
|
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
|
}
|
|
if (ret)
|
|
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
|
|
else
|
|
printk(KERN_INFO "Successfully put all powerdomains "
|
|
"to target state\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int omap3_pm_enter(suspend_state_t unused)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (suspend_state) {
|
|
case PM_SUSPEND_STANDBY:
|
|
case PM_SUSPEND_MEM:
|
|
ret = omap3_pm_suspend();
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Hooks to enable / disable UART interrupts during suspend */
|
|
static int omap3_pm_begin(suspend_state_t state)
|
|
{
|
|
disable_hlt();
|
|
suspend_state = state;
|
|
omap_uart_enable_irqs(0);
|
|
return 0;
|
|
}
|
|
|
|
static void omap3_pm_end(void)
|
|
{
|
|
suspend_state = PM_SUSPEND_ON;
|
|
omap_uart_enable_irqs(1);
|
|
enable_hlt();
|
|
return;
|
|
}
|
|
|
|
static struct platform_suspend_ops omap_pm_ops = {
|
|
.begin = omap3_pm_begin,
|
|
.end = omap3_pm_end,
|
|
.enter = omap3_pm_enter,
|
|
.valid = suspend_valid_only_mem,
|
|
};
|
|
#endif /* CONFIG_SUSPEND */
|
|
|
|
|
|
/**
|
|
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
|
|
* retention
|
|
*
|
|
* In cases where IVA2 is activated by bootcode, it may prevent
|
|
* full-chip retention or off-mode because it is not idle. This
|
|
* function forces the IVA2 into idle state so it can go
|
|
* into retention/off and thus allow full-chip retention/off.
|
|
*
|
|
**/
|
|
static void __init omap3_iva_idle(void)
|
|
{
|
|
/* ensure IVA2 clock is disabled */
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
/* if no clock activity, nothing else to do */
|
|
if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
|
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
|
return;
|
|
|
|
/* Reset IVA2 */
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
OMAP3430_RST3_IVA2_MASK,
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
|
|
|
/* Enable IVA2 clock */
|
|
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
|
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
/* Set IVA2 boot mode to 'idle' */
|
|
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
|
|
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
/* Un-reset IVA2 */
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
|
|
|
/* Disable IVA2 clock */
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
/* Reset IVA2 */
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
OMAP3430_RST3_IVA2_MASK,
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
|
}
|
|
|
|
static void __init omap3_d2d_idle(void)
|
|
{
|
|
u16 mask, padconf;
|
|
|
|
/* In a stand alone OMAP3430 where there is not a stacked
|
|
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
|
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
|
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
|
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
padconf |= mask;
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
padconf |= mask;
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
/* reset modem */
|
|
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
|
CORE_MOD, OMAP2_RM_RSTCTRL);
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
|
}
|
|
|
|
static void __init prcm_setup_regs(void)
|
|
{
|
|
u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
|
|
OMAP3630_AUTO_UART4_MASK : 0;
|
|
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
|
|
OMAP3630_EN_UART4_MASK : 0;
|
|
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
|
|
OMAP3630_GRPSEL_UART4_MASK : 0;
|
|
|
|
|
|
/* XXX Reset all wkdeps. This should be done when initializing
|
|
* powerdomains */
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
|
} else
|
|
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
|
|
|
|
/*
|
|
* Enable interface clock autoidle for all modules.
|
|
* Note that in the long run this should be done by clockfw
|
|
*/
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_MODEM_MASK |
|
|
OMAP3430ES2_AUTO_MMC3_MASK |
|
|
OMAP3430ES2_AUTO_ICR_MASK |
|
|
OMAP3430_AUTO_AES2_MASK |
|
|
OMAP3430_AUTO_SHA12_MASK |
|
|
OMAP3430_AUTO_DES2_MASK |
|
|
OMAP3430_AUTO_MMC2_MASK |
|
|
OMAP3430_AUTO_MMC1_MASK |
|
|
OMAP3430_AUTO_MSPRO_MASK |
|
|
OMAP3430_AUTO_HDQ_MASK |
|
|
OMAP3430_AUTO_MCSPI4_MASK |
|
|
OMAP3430_AUTO_MCSPI3_MASK |
|
|
OMAP3430_AUTO_MCSPI2_MASK |
|
|
OMAP3430_AUTO_MCSPI1_MASK |
|
|
OMAP3430_AUTO_I2C3_MASK |
|
|
OMAP3430_AUTO_I2C2_MASK |
|
|
OMAP3430_AUTO_I2C1_MASK |
|
|
OMAP3430_AUTO_UART2_MASK |
|
|
OMAP3430_AUTO_UART1_MASK |
|
|
OMAP3430_AUTO_GPT11_MASK |
|
|
OMAP3430_AUTO_GPT10_MASK |
|
|
OMAP3430_AUTO_MCBSP5_MASK |
|
|
OMAP3430_AUTO_MCBSP1_MASK |
|
|
OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
|
|
OMAP3430_AUTO_MAILBOXES_MASK |
|
|
OMAP3430_AUTO_OMAPCTRL_MASK |
|
|
OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
|
|
OMAP3430_AUTO_HSOTGUSB_MASK |
|
|
OMAP3430_AUTO_SAD2D_MASK |
|
|
OMAP3430_AUTO_SSI_MASK,
|
|
CORE_MOD, CM_AUTOIDLE1);
|
|
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_PKA_MASK |
|
|
OMAP3430_AUTO_AES1_MASK |
|
|
OMAP3430_AUTO_RNG_MASK |
|
|
OMAP3430_AUTO_SHA11_MASK |
|
|
OMAP3430_AUTO_DES1_MASK,
|
|
CORE_MOD, CM_AUTOIDLE2);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_MAD2D_MASK |
|
|
OMAP3430ES2_AUTO_USBTLL_MASK,
|
|
CORE_MOD, CM_AUTOIDLE3);
|
|
}
|
|
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_WDT2_MASK |
|
|
OMAP3430_AUTO_WDT1_MASK |
|
|
OMAP3430_AUTO_GPIO1_MASK |
|
|
OMAP3430_AUTO_32KSYNC_MASK |
|
|
OMAP3430_AUTO_GPT12_MASK |
|
|
OMAP3430_AUTO_GPT1_MASK,
|
|
WKUP_MOD, CM_AUTOIDLE);
|
|
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_DSS_MASK,
|
|
OMAP3430_DSS_MOD,
|
|
CM_AUTOIDLE);
|
|
|
|
cm_write_mod_reg(
|
|
OMAP3430_AUTO_CAM_MASK,
|
|
OMAP3430_CAM_MOD,
|
|
CM_AUTOIDLE);
|
|
|
|
cm_write_mod_reg(
|
|
omap3630_auto_uart4_mask |
|
|
OMAP3430_AUTO_GPIO6_MASK |
|
|
OMAP3430_AUTO_GPIO5_MASK |
|
|
OMAP3430_AUTO_GPIO4_MASK |
|
|
OMAP3430_AUTO_GPIO3_MASK |
|
|
OMAP3430_AUTO_GPIO2_MASK |
|
|
OMAP3430_AUTO_WDT3_MASK |
|
|
OMAP3430_AUTO_UART3_MASK |
|
|
OMAP3430_AUTO_GPT9_MASK |
|
|
OMAP3430_AUTO_GPT8_MASK |
|
|
OMAP3430_AUTO_GPT7_MASK |
|
|
OMAP3430_AUTO_GPT6_MASK |
|
|
OMAP3430_AUTO_GPT5_MASK |
|
|
OMAP3430_AUTO_GPT4_MASK |
|
|
OMAP3430_AUTO_GPT3_MASK |
|
|
OMAP3430_AUTO_GPT2_MASK |
|
|
OMAP3430_AUTO_MCBSP4_MASK |
|
|
OMAP3430_AUTO_MCBSP3_MASK |
|
|
OMAP3430_AUTO_MCBSP2_MASK,
|
|
OMAP3430_PER_MOD,
|
|
CM_AUTOIDLE);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
cm_write_mod_reg(
|
|
OMAP3430ES2_AUTO_USBHOST_MASK,
|
|
OMAP3430ES2_USBHOST_MOD,
|
|
CM_AUTOIDLE);
|
|
}
|
|
|
|
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
|
|
|
/*
|
|
* Set all plls to autoidle. This is needed until autoidle is
|
|
* enabled by clockfw
|
|
*/
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
|
|
OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
|
|
MPU_MOD,
|
|
CM_AUTOIDLE2);
|
|
cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
|
|
(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
|
|
PLL_MOD,
|
|
CM_AUTOIDLE);
|
|
cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
|
|
PLL_MOD,
|
|
CM_AUTOIDLE2);
|
|
|
|
/*
|
|
* Enable control of expternal oscillator through
|
|
* sys_clkreq. In the long run clock framework should
|
|
* take care of this.
|
|
*/
|
|
prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
|
OMAP3430_GR_MOD,
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
|
|
|
/* setup wakup source */
|
|
prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
|
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
|
WKUP_MOD, PM_WKEN);
|
|
/* No need to write EN_IO, that is always enabled */
|
|
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
|
OMAP3430_GRPSEL_GPT1_MASK |
|
|
OMAP3430_GRPSEL_GPT12_MASK,
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
/* For some reason IO doesn't generate wakeup event even if
|
|
* it is selected to mpu wakeup goup */
|
|
prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
|
|
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
|
|
|
/* Enable PM_WKEN to support DSS LPR */
|
|
prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
|
OMAP3430_DSS_MOD, PM_WKEN);
|
|
|
|
/* Enable wakeups in PER */
|
|
prm_write_mod_reg(omap3630_en_uart4_mask |
|
|
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
|
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
|
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
|
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
|
OMAP3430_EN_MCBSP4_MASK,
|
|
OMAP3430_PER_MOD, PM_WKEN);
|
|
/* and allow them to wake up MPU */
|
|
prm_write_mod_reg(omap3630_grpsel_uart4_mask |
|
|
OMAP3430_GRPSEL_GPIO2_MASK |
|
|
OMAP3430_GRPSEL_GPIO3_MASK |
|
|
OMAP3430_GRPSEL_GPIO4_MASK |
|
|
OMAP3430_GRPSEL_GPIO5_MASK |
|
|
OMAP3430_GRPSEL_GPIO6_MASK |
|
|
OMAP3430_GRPSEL_UART3_MASK |
|
|
OMAP3430_GRPSEL_MCBSP2_MASK |
|
|
OMAP3430_GRPSEL_MCBSP3_MASK |
|
|
OMAP3430_GRPSEL_MCBSP4_MASK,
|
|
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
/* Don't attach IVA interrupts */
|
|
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
/* Clear any pending 'reset' flags */
|
|
prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
|
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
|
|
|
/* Clear any pending PRCM interrupts */
|
|
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
omap3_iva_idle();
|
|
omap3_d2d_idle();
|
|
}
|
|
|
|
void omap3_pm_off_mode_enable(int enable)
|
|
{
|
|
struct power_state *pwrst;
|
|
u32 state;
|
|
|
|
if (enable)
|
|
state = PWRDM_POWER_OFF;
|
|
else
|
|
state = PWRDM_POWER_RET;
|
|
|
|
#ifdef CONFIG_CPU_IDLE
|
|
/*
|
|
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
|
|
* enable OFF mode in a stable form for previous revisions, restrict
|
|
* instead to RET
|
|
*/
|
|
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
|
|
omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
|
|
else
|
|
omap3_cpuidle_update_states(state, state);
|
|
#endif
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
|
|
pwrst->pwrdm == core_pwrdm &&
|
|
state == PWRDM_POWER_OFF) {
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
WARN_ONCE(1,
|
|
"%s: Core OFF disabled due to errata i583\n",
|
|
__func__);
|
|
} else {
|
|
pwrst->next_state = state;
|
|
}
|
|
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
}
|
|
}
|
|
|
|
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (pwrst->pwrdm == pwrdm)
|
|
return pwrst->next_state;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (pwrst->pwrdm == pwrdm) {
|
|
pwrst->next_state = state;
|
|
return 0;
|
|
}
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
if (!pwrdm->pwrsts)
|
|
return 0;
|
|
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
|
|
if (!pwrst)
|
|
return -ENOMEM;
|
|
pwrst->pwrdm = pwrdm;
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
list_add(&pwrst->node, &pwrst_list);
|
|
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
|
|
|
return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
}
|
|
|
|
/*
|
|
* Enable hw supervised mode for all clockdomains if it's
|
|
* supported. Initiate sleep transition for other clockdomains, if
|
|
* they are not used
|
|
*/
|
|
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
|
|
{
|
|
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
|
|
omap2_clkdm_allow_idle(clkdm);
|
|
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
|
|
atomic_read(&clkdm->usecount) == 0)
|
|
omap2_clkdm_sleep(clkdm);
|
|
return 0;
|
|
}
|
|
|
|
void omap_push_sram_idle(void)
|
|
{
|
|
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
|
|
omap34xx_cpu_suspend_sz);
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
|
|
_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
|
|
save_secure_ram_context_sz);
|
|
}
|
|
|
|
static void __init pm_errata_configure(void)
|
|
{
|
|
if (cpu_is_omap3630()) {
|
|
pm34xx_errata |= PM_RTA_ERRATUM_i608;
|
|
/* Enable the l2 cache toggling in sleep logic */
|
|
enable_omap3630_toggle_l2_on_restore();
|
|
if (omap_rev() < OMAP3630_REV_ES1_2)
|
|
pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
|
|
}
|
|
}
|
|
|
|
static int __init omap3_pm_init(void)
|
|
{
|
|
struct power_state *pwrst, *tmp;
|
|
struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
|
|
int ret;
|
|
|
|
if (!cpu_is_omap34xx())
|
|
return -ENODEV;
|
|
|
|
pm_errata_configure();
|
|
|
|
printk(KERN_ERR "Power Management for TI OMAP3.\n");
|
|
|
|
/* XXX prcm_setup_regs needs to be before enabling hw
|
|
* supervised mode for powerdomains */
|
|
prcm_setup_regs();
|
|
|
|
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
|
|
(irq_handler_t)prcm_interrupt_handler,
|
|
IRQF_DISABLED, "prcm", NULL);
|
|
if (ret) {
|
|
printk(KERN_ERR "request_irq failed to register for 0x%x\n",
|
|
INT_34XX_PRCM_MPU_IRQ);
|
|
goto err1;
|
|
}
|
|
|
|
ret = pwrdm_for_each(pwrdms_setup, NULL);
|
|
if (ret) {
|
|
printk(KERN_ERR "Failed to setup powerdomains\n");
|
|
goto err2;
|
|
}
|
|
|
|
(void) clkdm_for_each(clkdms_setup, NULL);
|
|
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
|
if (mpu_pwrdm == NULL) {
|
|
printk(KERN_ERR "Failed to get mpu_pwrdm\n");
|
|
goto err2;
|
|
}
|
|
|
|
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
|
|
per_pwrdm = pwrdm_lookup("per_pwrdm");
|
|
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
|
cam_pwrdm = pwrdm_lookup("cam_pwrdm");
|
|
|
|
neon_clkdm = clkdm_lookup("neon_clkdm");
|
|
mpu_clkdm = clkdm_lookup("mpu_clkdm");
|
|
per_clkdm = clkdm_lookup("per_clkdm");
|
|
core_clkdm = clkdm_lookup("core_clkdm");
|
|
|
|
omap_push_sram_idle();
|
|
#ifdef CONFIG_SUSPEND
|
|
suspend_set_ops(&omap_pm_ops);
|
|
#endif /* CONFIG_SUSPEND */
|
|
|
|
pm_idle = omap3_pm_idle;
|
|
omap3_idle_init();
|
|
|
|
/*
|
|
* RTA is disabled during initialization as per erratum i608
|
|
* it is safer to disable RTA by the bootloader, but we would like
|
|
* to be doubly sure here and prevent any mishaps.
|
|
*/
|
|
if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
|
|
omap3630_ctrl_disable_rta();
|
|
|
|
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
|
|
omap3_secure_ram_storage =
|
|
kmalloc(0x803F, GFP_KERNEL);
|
|
if (!omap3_secure_ram_storage)
|
|
printk(KERN_ERR "Memory allocation failed when"
|
|
"allocating for secure sram context\n");
|
|
|
|
local_irq_disable();
|
|
local_fiq_disable();
|
|
|
|
omap_dma_global_context_save();
|
|
omap3_save_secure_ram_context(PWRDM_POWER_ON);
|
|
omap_dma_global_context_restore();
|
|
|
|
local_irq_enable();
|
|
local_fiq_enable();
|
|
}
|
|
|
|
omap3_save_scratchpad_contents();
|
|
err1:
|
|
return ret;
|
|
err2:
|
|
free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
|
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
|
|
list_del(&pwrst->node);
|
|
kfree(pwrst);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
late_initcall(omap3_pm_init);
|