84c3d4aaec
Manual merge of: arch/powerpc/Kconfig arch/powerpc/kernel/stacktrace.c arch/powerpc/mm/slice.c arch/ppc/kernel/smp.c
438 lines
9.9 KiB
C
438 lines
9.9 KiB
C
/*
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* (C) Copyright 2003-2004
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* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
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* This is a combined i2c adapter and algorithm driver for the
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* MPC107/Tsi107 PowerPC northbridge and processors that include
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* the same I2C unit (8240, 8245, 85xx).
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*
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* Release 0.8
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/of_i2c.h>
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#include <asm/io.h>
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#include <linux/fsl_devices.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#define DRV_NAME "mpc-i2c"
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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#define MPC_I2C_DR 0x10
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#define MPC_I2C_DFSRR 0x14
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#define CCR_MEN 0x80
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#define CCR_MIEN 0x40
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#define CCR_MSTA 0x20
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#define CCR_MTX 0x10
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#define CCR_TXAK 0x08
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#define CCR_RSTA 0x04
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#define CSR_MCF 0x80
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#define CSR_MAAS 0x40
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#define CSR_MBB 0x20
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#define CSR_MAL 0x10
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#define CSR_SRW 0x04
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#define CSR_MIF 0x02
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#define CSR_RXAK 0x01
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struct mpc_i2c {
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void __iomem *base;
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u32 interrupt;
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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u32 flags;
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};
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static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
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{
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writeb(x, i2c->base + MPC_I2C_CR);
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}
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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{
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struct mpc_i2c *i2c = dev_id;
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if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
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/* Read again to allow register to stabilise */
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i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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wake_up_interruptible(&i2c->queue);
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}
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return IRQ_HANDLED;
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}
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/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
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* the bus, because it wants to send ACK.
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* Following sequence of enabling/disabling and sending start/stop generates
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* the pulse, so it's all OK.
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*/
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static void mpc_i2c_fixup(struct mpc_i2c *i2c)
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{
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writeccr(i2c, 0);
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udelay(30);
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writeccr(i2c, CCR_MEN);
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udelay(30);
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writeccr(i2c, CCR_MSTA | CCR_MTX);
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udelay(30);
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writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
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udelay(30);
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writeccr(i2c, CCR_MEN);
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udelay(30);
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}
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static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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{
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unsigned long orig_jiffies = jiffies;
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u32 x;
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int result = 0;
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if (i2c->irq == NO_IRQ)
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{
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while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
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schedule();
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if (time_after(jiffies, orig_jiffies + timeout)) {
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pr_debug("I2C: timeout\n");
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writeccr(i2c, 0);
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result = -EIO;
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break;
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}
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}
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x = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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} else {
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/* Interrupt mode */
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result = wait_event_interruptible_timeout(i2c->queue,
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(i2c->interrupt & CSR_MIF), timeout * HZ);
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if (unlikely(result < 0)) {
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pr_debug("I2C: wait interrupted\n");
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writeccr(i2c, 0);
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} else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
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pr_debug("I2C: wait timeout\n");
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writeccr(i2c, 0);
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result = -ETIMEDOUT;
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}
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x = i2c->interrupt;
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i2c->interrupt = 0;
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}
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if (result < 0)
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return result;
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if (!(x & CSR_MCF)) {
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pr_debug("I2C: unfinished\n");
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return -EIO;
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}
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if (x & CSR_MAL) {
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pr_debug("I2C: MAL\n");
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return -EIO;
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}
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if (writing && (x & CSR_RXAK)) {
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pr_debug("I2C: No RXAK\n");
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/* generate stop */
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writeccr(i2c, CCR_MEN);
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return -EIO;
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}
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return 0;
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}
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static void mpc_i2c_setclock(struct mpc_i2c *i2c)
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{
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/* Set clock and filters */
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if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
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writeb(0x31, i2c->base + MPC_I2C_FDR);
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writeb(0x10, i2c->base + MPC_I2C_DFSRR);
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} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
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writeb(0x3f, i2c->base + MPC_I2C_FDR);
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else
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writel(0x1031, i2c->base + MPC_I2C_FDR);
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}
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static void mpc_i2c_start(struct mpc_i2c *i2c)
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{
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/* Clear arbitration */
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writeb(0, i2c->base + MPC_I2C_SR);
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/* Start with MEN */
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writeccr(i2c, CCR_MEN);
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}
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static void mpc_i2c_stop(struct mpc_i2c *i2c)
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{
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writeccr(i2c, CCR_MEN);
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}
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static int mpc_write(struct mpc_i2c *i2c, int target,
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const u8 * data, int length, int restart)
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{
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int i, result;
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unsigned timeout = i2c->adap.timeout;
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u32 flags = restart ? CCR_RSTA : 0;
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/* Start with MEN */
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if (!restart)
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writeccr(i2c, CCR_MEN);
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/* Start as master */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target byte */
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writeb((target << 1), i2c->base + MPC_I2C_DR);
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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for (i = 0; i < length; i++) {
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/* Write data byte */
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writeb(data[i], i2c->base + MPC_I2C_DR);
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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}
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return 0;
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}
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static int mpc_read(struct mpc_i2c *i2c, int target,
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u8 * data, int length, int restart)
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{
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unsigned timeout = i2c->adap.timeout;
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int i, result;
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u32 flags = restart ? CCR_RSTA : 0;
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/* Start with MEN */
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if (!restart)
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writeccr(i2c, CCR_MEN);
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/* Switch to read - restart */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target address byte - this time with the read flag set */
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writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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if (length) {
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if (length == 1)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
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else
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
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/* Dummy read */
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readb(i2c->base + MPC_I2C_DR);
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}
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for (i = 0; i < length; i++) {
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result = i2c_wait(i2c, timeout, 0);
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if (result < 0)
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return result;
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/* Generate txack on next to last byte */
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if (i == length - 2)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
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/* Generate stop on last byte */
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if (i == length - 1)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
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data[i] = readb(i2c->base + MPC_I2C_DR);
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}
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return length;
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}
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static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct i2c_msg *pmsg;
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int i;
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int ret = 0;
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unsigned long orig_jiffies = jiffies;
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struct mpc_i2c *i2c = i2c_get_adapdata(adap);
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mpc_i2c_start(i2c);
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/* Allow bus up to 1s to become not busy */
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while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
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if (signal_pending(current)) {
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pr_debug("I2C: Interrupted\n");
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writeccr(i2c, 0);
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return -EINTR;
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}
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if (time_after(jiffies, orig_jiffies + HZ)) {
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pr_debug("I2C: timeout\n");
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if (readb(i2c->base + MPC_I2C_SR) ==
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(CSR_MCF | CSR_MBB | CSR_RXAK))
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mpc_i2c_fixup(i2c);
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return -EIO;
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}
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schedule();
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}
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for (i = 0; ret >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
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pmsg->flags & I2C_M_RD ? "read" : "write",
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pmsg->len, pmsg->addr, i + 1, num);
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if (pmsg->flags & I2C_M_RD)
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ret =
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mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
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else
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ret =
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mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
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}
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mpc_i2c_stop(i2c);
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return (ret < 0) ? ret : num;
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}
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static u32 mpc_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm mpc_algo = {
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.master_xfer = mpc_xfer,
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.functionality = mpc_functionality,
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};
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static struct i2c_adapter mpc_ops = {
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.owner = THIS_MODULE,
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.name = "MPC adapter",
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.id = I2C_HW_MPC107,
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.algo = &mpc_algo,
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.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
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.timeout = 1,
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};
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static int __devinit fsl_i2c_probe(struct of_device *op, const struct of_device_id *match)
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{
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int result = 0;
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struct mpc_i2c *i2c;
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i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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if (of_get_property(op->node, "dfsrr", NULL))
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i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
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if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
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of_device_is_compatible(op->node, "mpc5200-i2c"))
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i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
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init_waitqueue_head(&i2c->queue);
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i2c->base = of_iomap(op->node, 0);
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if (!i2c->base) {
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printk(KERN_ERR "i2c-mpc - failed to map controller\n");
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result = -ENOMEM;
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goto fail_map;
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}
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i2c->irq = irq_of_parse_and_map(op->node, 0);
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if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
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result = request_irq(i2c->irq, mpc_i2c_isr,
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IRQF_SHARED, "i2c-mpc", i2c);
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if (result < 0) {
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printk(KERN_ERR "i2c-mpc - failed to attach interrupt\n");
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goto fail_request;
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}
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}
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mpc_i2c_setclock(i2c);
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dev_set_drvdata(&op->dev, i2c);
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i2c->adap = mpc_ops;
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i2c_set_adapdata(&i2c->adap, i2c);
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i2c->adap.dev.parent = &op->dev;
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result = i2c_add_adapter(&i2c->adap);
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if (result < 0) {
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printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
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goto fail_add;
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}
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of_register_i2c_devices(&i2c->adap, op->node);
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return result;
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fail_add:
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dev_set_drvdata(&op->dev, NULL);
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free_irq(i2c->irq, i2c);
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fail_request:
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irq_dispose_mapping(i2c->irq);
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iounmap(i2c->base);
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fail_map:
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kfree(i2c);
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return result;
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};
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static int __devexit fsl_i2c_remove(struct of_device *op)
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{
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struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
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i2c_del_adapter(&i2c->adap);
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dev_set_drvdata(&op->dev, NULL);
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if (i2c->irq != NO_IRQ)
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free_irq(i2c->irq, i2c);
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irq_dispose_mapping(i2c->irq);
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iounmap(i2c->base);
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kfree(i2c);
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return 0;
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};
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static const struct of_device_id mpc_i2c_of_match[] = {
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{.compatible = "fsl-i2c",},
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{},
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};
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MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
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/* Structure for a device driver */
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static struct of_platform_driver mpc_i2c_driver = {
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.match_table = mpc_i2c_of_match,
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.probe = fsl_i2c_probe,
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.remove = __devexit_p(fsl_i2c_remove),
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.driver = {
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.owner = THIS_MODULE,
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.name = DRV_NAME,
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},
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};
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static int __init fsl_i2c_init(void)
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{
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int rv;
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rv = of_register_platform_driver(&mpc_i2c_driver);
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if (rv)
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printk(KERN_ERR DRV_NAME
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" of_register_platform_driver failed (%i)\n", rv);
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return rv;
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}
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static void __exit fsl_i2c_exit(void)
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{
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of_unregister_platform_driver(&mpc_i2c_driver);
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}
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module_init(fsl_i2c_init);
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module_exit(fsl_i2c_exit);
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MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
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MODULE_DESCRIPTION
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("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
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MODULE_LICENSE("GPL");
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