7e4f943b72
Do not allow applications to use the full buffer found on McBSP1,3,4,5. Using the full buffer in threshold mode causes the McBSP buffer to run dry, which can be observed as channels are switching (in reality the channels are shifting). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
203 lines
5.4 KiB
C
203 lines
5.4 KiB
C
/*
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* linux/arch/arm/mach-omap2/mcbsp.c
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*
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* Copyright (C) 2008 Instituto Nokia de Tecnologia
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* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Multichannel mode not supported.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <mach/irqs.h>
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#include <mach/dma.h>
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#include <mach/irqs.h>
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#include <mach/mux.h>
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#include <mach/cpu.h>
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#include <mach/mcbsp.h>
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static void omap2_mcbsp2_mux_setup(void)
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{
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omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
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omap_cfg_reg(R14_24XX_MCBSP2_FSX);
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omap_cfg_reg(W15_24XX_MCBSP2_DR);
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omap_cfg_reg(V15_24XX_MCBSP2_DX);
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omap_cfg_reg(V14_24XX_GPIO117);
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/*
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* TODO: Need to add MUX settings for OMAP 2430 SDP
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*/
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}
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static void omap2_mcbsp_request(unsigned int id)
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{
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if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
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omap2_mcbsp2_mux_setup();
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}
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static struct omap_mcbsp_ops omap2_mcbsp_ops = {
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.request = omap2_mcbsp_request,
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};
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#ifdef CONFIG_ARCH_OMAP2420
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static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
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{
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.phys_base = OMAP24XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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{
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.phys_base = OMAP24XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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};
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#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
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#else
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#define omap2420_mcbsp_pdata NULL
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#define OMAP2420_MCBSP_PDATA_SZ 0
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
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{
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.phys_base = OMAP24XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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{
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.phys_base = OMAP24XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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{
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.phys_base = OMAP2430_MCBSP3_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
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.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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{
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.phys_base = OMAP2430_MCBSP4_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
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.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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{
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.phys_base = OMAP2430_MCBSP5_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
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.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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},
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};
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#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
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#else
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#define omap2430_mcbsp_pdata NULL
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#define OMAP2430_MCBSP_PDATA_SZ 0
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
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{
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.phys_base = OMAP34XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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.buffer_size = 0x6F,
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},
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{
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.phys_base = OMAP34XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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.buffer_size = 0x3FF,
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},
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{
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.phys_base = OMAP34XX_MCBSP3_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
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.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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.buffer_size = 0x6F,
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},
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{
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.phys_base = OMAP34XX_MCBSP4_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
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.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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.buffer_size = 0x6F,
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},
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{
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.phys_base = OMAP34XX_MCBSP5_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
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.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
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.ops = &omap2_mcbsp_ops,
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.buffer_size = 0x6F,
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},
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};
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#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
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#else
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#define omap34xx_mcbsp_pdata NULL
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#define OMAP34XX_MCBSP_PDATA_SZ 0
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#endif
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static int __init omap2_mcbsp_init(void)
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{
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if (cpu_is_omap2420())
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omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
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if (cpu_is_omap2430())
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omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
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if (cpu_is_omap34xx())
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omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
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mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
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GFP_KERNEL);
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if (!mcbsp_ptr)
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return -ENOMEM;
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if (cpu_is_omap2420())
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omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
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OMAP2420_MCBSP_PDATA_SZ);
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if (cpu_is_omap2430())
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omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
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OMAP2430_MCBSP_PDATA_SZ);
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if (cpu_is_omap34xx())
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omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
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OMAP34XX_MCBSP_PDATA_SZ);
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return omap_mcbsp_init();
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}
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arch_initcall(omap2_mcbsp_init);
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