e9b72e43d9
Patch from Lennert Buytenhek Switch the users of ixp2000_reg_write that depend on writes being flushed out of the write buffer by the time that function returns over to ixp2000_reg_wrb. When using XCB=101, writes to the same functional unit are still guaranteed to complete in order, so we only need to protect against: - reordering of writes to different functional units - masking an interrupt and then reenabling the IRQ bit in CPSR Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/*
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* linux/include/asm-arm/arch-ixp2000/system.h
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*
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* Copyright (C) 2002 Intel Corp.
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* Copyricht (C) 2003-2005 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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}
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static inline void arch_reset(char mode)
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{
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local_irq_disable();
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/*
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* Reset flash banking register so that we are pointing at
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* RedBoot bank.
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*/
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if (machine_is_ixdp2401()) {
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ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
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((0 >> IXDP2X01_FLASH_WINDOW_BITS)
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| IXDP2X01_CPLD_FLASH_INTERN));
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ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
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}
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/*
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* On IXDP2801 we need to write this magic sequence to the CPLD
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* to cause a complete reset of the CPU and all external devices
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* and move the flash bank register back to 0.
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*/
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if (machine_is_ixdp2801()) {
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unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
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reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
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ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
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ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
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}
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ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
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}
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