5c01d56693
Conflicts: Documentation/feature-removal-schedule.txt drivers/net/wireless/ath/ath5k/phy.c drivers/net/wireless/wl12xx/wl1271_main.c
688 lines
20 KiB
C
688 lines
20 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/etherdevice.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <net/mac80211.h>
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#include "iwl-eeprom.h"
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-sta.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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/**
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* iwl_txq_update_write_ptr - Send new write index to hardware
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*/
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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u32 reg = 0;
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int txq_id = txq->q.id;
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if (txq->need_update == 0)
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return;
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/* if we're trying to save power */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
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txq_id, reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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}
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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/* else not in power-save mode, uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx). */
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} else
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iwl_write32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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txq->need_update = 0;
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}
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EXPORT_SYMBOL(iwl_txq_update_write_ptr);
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void iwl_free_tfds_in_queue(struct iwl_priv *priv,
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int sta_id, int tid, int freed)
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{
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if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
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priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
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else {
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IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
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priv->stations[sta_id].tid[tid].tfds_in_queue,
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freed);
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priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
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}
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}
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EXPORT_SYMBOL(iwl_free_tfds_in_queue);
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/**
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* iwl_tx_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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*
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* Empty queue by removing and destroying all BD's.
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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struct device *dev = &priv->pci_dev->dev;
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int i;
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if (q->n_bd == 0)
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return;
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/* first, empty all BD's */
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for (; q->write_ptr != q->read_ptr;
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
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priv->cfg->ops->lib->txq_free_tfd(priv, txq);
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/* De-alloc array of command/tx buffers */
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for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd)
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dma_free_coherent(dev, priv->hw_params.tfd_size *
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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/* De-alloc array of per-TFD driver data */
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kfree(txq->txb);
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txq->txb = NULL;
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/* deallocate arrays */
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kfree(txq->cmd);
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kfree(txq->meta);
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txq->cmd = NULL;
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txq->meta = NULL;
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/* 0-fill queue descriptor structure */
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memset(txq, 0, sizeof(*txq));
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}
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EXPORT_SYMBOL(iwl_tx_queue_free);
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/**
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* iwl_cmd_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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*
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* Empty queue by removing and destroying all BD's.
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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void iwl_cmd_queue_free(struct iwl_priv *priv)
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{
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struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
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struct iwl_queue *q = &txq->q;
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struct device *dev = &priv->pci_dev->dev;
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int i;
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bool huge = false;
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if (q->n_bd == 0)
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return;
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for (; q->read_ptr != q->write_ptr;
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
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/* we have no way to tell if it is a huge cmd ATM */
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i = get_cmd_index(q, q->read_ptr, 0);
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if (txq->meta[i].flags & CMD_SIZE_HUGE) {
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huge = true;
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continue;
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}
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pci_unmap_single(priv->pci_dev,
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pci_unmap_addr(&txq->meta[i], mapping),
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pci_unmap_len(&txq->meta[i], len),
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PCI_DMA_BIDIRECTIONAL);
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}
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if (huge) {
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i = q->n_window;
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pci_unmap_single(priv->pci_dev,
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pci_unmap_addr(&txq->meta[i], mapping),
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pci_unmap_len(&txq->meta[i], len),
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PCI_DMA_BIDIRECTIONAL);
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}
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/* De-alloc array of command/tx buffers */
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for (i = 0; i <= TFD_CMD_SLOTS; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd)
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dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
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txq->tfds, txq->q.dma_addr);
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/* deallocate arrays */
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kfree(txq->cmd);
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kfree(txq->meta);
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txq->cmd = NULL;
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txq->meta = NULL;
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/* 0-fill queue descriptor structure */
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memset(txq, 0, sizeof(*txq));
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}
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EXPORT_SYMBOL(iwl_cmd_queue_free);
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/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
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* DMA services
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*
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* Theory of operation
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*
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* A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
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* of buffer descriptors, each of which points to one or more data buffers for
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* the device to read from or fill. Driver and device exchange status of each
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* queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
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* entries in each circular buffer, to protect against confusing empty and full
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* queue states.
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*
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* The device reads or writes the data in the queues via the device's several
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* DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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*
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* For Tx queue, there are low mark and high mark limits. If, after queuing
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* the packet for Tx, free space become < low mark, Tx queue stopped. When
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* reclaiming packets (on 'tx done IRQ), if free space become > high mark,
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* Tx queue resumed.
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*
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* See more detailed info in iwl-4965-hw.h.
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***************************************************/
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int iwl_queue_space(const struct iwl_queue *q)
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{
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int s = q->read_ptr - q->write_ptr;
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if (q->read_ptr > q->write_ptr)
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s -= q->n_bd;
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if (s <= 0)
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s += q->n_window;
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/* keep some reserve to not confuse empty and full situations */
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s -= 2;
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if (s < 0)
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s = 0;
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return s;
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}
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EXPORT_SYMBOL(iwl_queue_space);
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/**
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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*/
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static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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int count, int slots_num, u32 id)
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{
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q->n_bd = count;
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q->n_window = slots_num;
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q->id = id;
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/* count must be power-of-two size, otherwise iwl_queue_inc_wrap
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* and iwl_queue_dec_wrap are broken. */
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BUG_ON(!is_power_of_2(count));
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/* slots_num must be power-of-two size, otherwise
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* get_cmd_index is broken. */
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BUG_ON(!is_power_of_2(slots_num));
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q->low_mark = q->n_window / 4;
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if (q->low_mark < 4)
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q->low_mark = 4;
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q->high_mark = q->n_window / 8;
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if (q->high_mark < 2)
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q->high_mark = 2;
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q->write_ptr = q->read_ptr = 0;
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q->last_read_ptr = 0;
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q->repeat_same_read_ptr = 0;
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return 0;
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}
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/**
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* iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
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*/
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static int iwl_tx_queue_alloc(struct iwl_priv *priv,
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struct iwl_tx_queue *txq, u32 id)
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{
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struct device *dev = &priv->pci_dev->dev;
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size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
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/* Driver private data, only for Tx (not command) queues,
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* not shared with device. */
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if (id != IWL_CMD_QUEUE_NUM) {
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txq->txb = kmalloc(sizeof(txq->txb[0]) *
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TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
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if (!txq->txb) {
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IWL_ERR(priv, "kmalloc for auxiliary BD "
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"structures failed\n");
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goto error;
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}
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} else {
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txq->txb = NULL;
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}
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/* Circular buffer of transmit frame descriptors (TFDs),
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* shared with device */
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txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
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GFP_KERNEL);
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if (!txq->tfds) {
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IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
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goto error;
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}
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txq->q.id = id;
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return 0;
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error:
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kfree(txq->txb);
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txq->txb = NULL;
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return -ENOMEM;
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}
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/**
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* iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
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*/
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int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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int slots_num, u32 txq_id)
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{
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int i, len;
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int ret;
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int actual_slots = slots_num;
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/*
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* Alloc buffer array for commands (Tx or other types of commands).
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* For the command queue (#4), allocate command space + one big
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* command for scan, since scan command is very huge; the system will
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* not have two scans at the same time, so only one is needed.
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* For normal Tx queues (all other queues), no super-size command
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* space is needed.
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*/
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if (txq_id == IWL_CMD_QUEUE_NUM)
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actual_slots++;
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txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
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GFP_KERNEL);
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txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
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GFP_KERNEL);
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if (!txq->meta || !txq->cmd)
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goto out_free_arrays;
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len = sizeof(struct iwl_device_cmd);
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for (i = 0; i < actual_slots; i++) {
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/* only happens for cmd queue */
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if (i == slots_num)
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len = IWL_MAX_CMD_SIZE;
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txq->cmd[i] = kmalloc(len, GFP_KERNEL);
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if (!txq->cmd[i])
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goto err;
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}
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/* Alloc driver data array and TFD circular buffer */
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ret = iwl_tx_queue_alloc(priv, txq, txq_id);
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if (ret)
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goto err;
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txq->need_update = 0;
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/*
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* Aggregation TX queues will get their ID when aggregation begins;
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* they overwrite the setting done here. The command FIFO doesn't
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* need an swq_id so don't set one to catch errors, all others can
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* be set up to the identity mapping.
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*/
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if (txq_id != IWL_CMD_QUEUE_NUM)
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txq->swq_id = txq_id;
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/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
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* iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
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BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
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/* Initialize queue's high/low-water marks, and head/tail indexes */
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iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
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/* Tell device where to find queue */
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priv->cfg->ops->lib->txq_init(priv, txq);
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return 0;
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err:
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for (i = 0; i < actual_slots; i++)
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kfree(txq->cmd[i]);
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out_free_arrays:
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kfree(txq->meta);
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kfree(txq->cmd);
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return -ENOMEM;
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}
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EXPORT_SYMBOL(iwl_tx_queue_init);
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void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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int slots_num, u32 txq_id)
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{
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int actual_slots = slots_num;
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if (txq_id == IWL_CMD_QUEUE_NUM)
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actual_slots++;
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memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
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txq->need_update = 0;
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/* Initialize queue's high/low-water marks, and head/tail indexes */
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iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
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/* Tell device where to find queue */
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priv->cfg->ops->lib->txq_init(priv, txq);
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}
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EXPORT_SYMBOL(iwl_tx_queue_reset);
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/*************** HOST COMMAND QUEUE FUNCTIONS *****/
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/**
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* iwl_enqueue_hcmd - enqueue a uCode command
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* @priv: device private data point
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* @cmd: a point to the ucode command structure
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*
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* The function returns < 0 values to indicate the operation is
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* failed. On success, it turns the index (> 0) of command in the
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* command queue.
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*/
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int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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{
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struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
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struct iwl_queue *q = &txq->q;
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struct iwl_device_cmd *out_cmd;
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struct iwl_cmd_meta *out_meta;
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dma_addr_t phys_addr;
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unsigned long flags;
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int len;
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u32 idx;
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u16 fix_size;
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cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
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fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
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/* If any of the command structures end up being larger than
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* the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
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* we will need to increase the size of the TFD entries
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* Also, check to see if command buffer should not exceed the size
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* of device_cmd and max_cmd_size. */
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BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
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!(cmd->flags & CMD_SIZE_HUGE));
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BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
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if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
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IWL_WARN(priv, "Not sending command - %s KILL\n",
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iwl_is_rfkill(priv) ? "RF" : "CT");
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return -EIO;
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}
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if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
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IWL_ERR(priv, "No space in command queue\n");
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if (iwl_within_ct_kill_margin(priv))
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iwl_tt_enter_ct_kill(priv);
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else {
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IWL_ERR(priv, "Restarting adapter due to queue full\n");
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queue_work(priv->workqueue, &priv->restart);
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}
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return -ENOSPC;
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}
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spin_lock_irqsave(&priv->hcmd_lock, flags);
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/* If this is a huge cmd, mark the huge flag also on the meta.flags
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* of the _original_ cmd. This is used for DMA mapping clean up.
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*/
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if (cmd->flags & CMD_SIZE_HUGE) {
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idx = get_cmd_index(q, q->write_ptr, 0);
|
|
txq->meta[idx].flags = CMD_SIZE_HUGE;
|
|
}
|
|
|
|
idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
|
|
out_cmd = txq->cmd[idx];
|
|
out_meta = &txq->meta[idx];
|
|
|
|
memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
|
|
out_meta->flags = cmd->flags;
|
|
if (cmd->flags & CMD_WANT_SKB)
|
|
out_meta->source = cmd;
|
|
if (cmd->flags & CMD_ASYNC)
|
|
out_meta->callback = cmd->callback;
|
|
|
|
out_cmd->hdr.cmd = cmd->id;
|
|
memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
|
|
|
|
/* At this point, the out_cmd now has all of the incoming cmd
|
|
* information */
|
|
|
|
out_cmd->hdr.flags = 0;
|
|
out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
|
|
INDEX_TO_SEQ(q->write_ptr));
|
|
if (cmd->flags & CMD_SIZE_HUGE)
|
|
out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
|
|
len = sizeof(struct iwl_device_cmd);
|
|
if (idx == TFD_CMD_SLOTS)
|
|
len = IWL_MAX_CMD_SIZE;
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
switch (out_cmd->hdr.cmd) {
|
|
case REPLY_TX_LINK_QUALITY_CMD:
|
|
case SENSITIVITY_CMD:
|
|
IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
|
|
"%d bytes at %d[%d]:%d\n",
|
|
get_cmd_string(out_cmd->hdr.cmd),
|
|
out_cmd->hdr.cmd,
|
|
le16_to_cpu(out_cmd->hdr.sequence), fix_size,
|
|
q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
|
|
break;
|
|
default:
|
|
IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
|
|
"%d bytes at %d[%d]:%d\n",
|
|
get_cmd_string(out_cmd->hdr.cmd),
|
|
out_cmd->hdr.cmd,
|
|
le16_to_cpu(out_cmd->hdr.sequence), fix_size,
|
|
q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
|
|
}
|
|
#endif
|
|
txq->need_update = 1;
|
|
|
|
if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
|
|
/* Set up entry in queue's byte count circular buffer */
|
|
priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
|
|
|
|
phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
|
|
fix_size, PCI_DMA_BIDIRECTIONAL);
|
|
pci_unmap_addr_set(out_meta, mapping, phys_addr);
|
|
pci_unmap_len_set(out_meta, len, fix_size);
|
|
|
|
trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
|
|
|
|
priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
|
|
phys_addr, fix_size, 1,
|
|
U32_PAD(cmd->len));
|
|
|
|
/* Increment and update queue's write index */
|
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
|
iwl_txq_update_write_ptr(priv, txq);
|
|
|
|
spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
return idx;
|
|
}
|
|
|
|
/**
|
|
* iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
|
|
*
|
|
* When FW advances 'R' index, all entries between old and new 'R' index
|
|
* need to be reclaimed. As result, some free space forms. If there is
|
|
* enough free space (> low mark), wake the stack that feeds us.
|
|
*/
|
|
static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
|
|
int idx, int cmd_idx)
|
|
{
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
struct iwl_queue *q = &txq->q;
|
|
int nfreed = 0;
|
|
|
|
if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
|
|
IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
|
|
"is out of range [0-%d] %d %d.\n", txq_id,
|
|
idx, q->n_bd, q->write_ptr, q->read_ptr);
|
|
return;
|
|
}
|
|
|
|
for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
|
|
q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
|
|
|
|
if (nfreed++ > 0) {
|
|
IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
|
|
q->write_ptr, q->read_ptr);
|
|
queue_work(priv->workqueue, &priv->restart);
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/**
|
|
* iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
|
|
* @rxb: Rx buffer to reclaim
|
|
*
|
|
* If an Rx buffer has an async callback associated with it the callback
|
|
* will be executed. The attached skb (if present) will only be freed
|
|
* if the callback returns 1
|
|
*/
|
|
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
|
{
|
|
struct iwl_rx_packet *pkt = rxb_addr(rxb);
|
|
u16 sequence = le16_to_cpu(pkt->hdr.sequence);
|
|
int txq_id = SEQ_TO_QUEUE(sequence);
|
|
int index = SEQ_TO_INDEX(sequence);
|
|
int cmd_index;
|
|
bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
|
|
struct iwl_device_cmd *cmd;
|
|
struct iwl_cmd_meta *meta;
|
|
struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
|
|
|
|
/* If a Tx command is being handled and it isn't in the actual
|
|
* command queue then there a command routing bug has been introduced
|
|
* in the queue management code. */
|
|
if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
|
|
"wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
|
|
txq_id, sequence,
|
|
priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
|
|
priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
|
|
iwl_print_hex_error(priv, pkt, 32);
|
|
return;
|
|
}
|
|
|
|
/* If this is a huge cmd, clear the huge flag on the meta.flags
|
|
* of the _original_ cmd. So that iwl_cmd_queue_free won't unmap
|
|
* the DMA buffer for the scan (huge) command.
|
|
*/
|
|
if (huge) {
|
|
cmd_index = get_cmd_index(&txq->q, index, 0);
|
|
txq->meta[cmd_index].flags = 0;
|
|
}
|
|
cmd_index = get_cmd_index(&txq->q, index, huge);
|
|
cmd = txq->cmd[cmd_index];
|
|
meta = &txq->meta[cmd_index];
|
|
|
|
pci_unmap_single(priv->pci_dev,
|
|
pci_unmap_addr(meta, mapping),
|
|
pci_unmap_len(meta, len),
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
/* Input error checking is done when commands are added to queue. */
|
|
if (meta->flags & CMD_WANT_SKB) {
|
|
meta->source->reply_page = (unsigned long)rxb_addr(rxb);
|
|
rxb->page = NULL;
|
|
} else if (meta->callback)
|
|
meta->callback(priv, cmd, pkt);
|
|
|
|
iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
|
|
|
|
if (!(meta->flags & CMD_ASYNC)) {
|
|
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
|
|
get_cmd_string(cmd->hdr.cmd));
|
|
wake_up_interruptible(&priv->wait_command_queue);
|
|
}
|
|
meta->flags = 0;
|
|
}
|
|
EXPORT_SYMBOL(iwl_tx_cmd_complete);
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
|
|
#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
|
|
|
|
const char *iwl_get_tx_fail_reason(u32 status)
|
|
{
|
|
switch (status & TX_STATUS_MSK) {
|
|
case TX_STATUS_SUCCESS:
|
|
return "SUCCESS";
|
|
TX_STATUS_POSTPONE(DELAY);
|
|
TX_STATUS_POSTPONE(FEW_BYTES);
|
|
TX_STATUS_POSTPONE(BT_PRIO);
|
|
TX_STATUS_POSTPONE(QUIET_PERIOD);
|
|
TX_STATUS_POSTPONE(CALC_TTAK);
|
|
TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
|
|
TX_STATUS_FAIL(SHORT_LIMIT);
|
|
TX_STATUS_FAIL(LONG_LIMIT);
|
|
TX_STATUS_FAIL(FIFO_UNDERRUN);
|
|
TX_STATUS_FAIL(DRAIN_FLOW);
|
|
TX_STATUS_FAIL(RFKILL_FLUSH);
|
|
TX_STATUS_FAIL(LIFE_EXPIRE);
|
|
TX_STATUS_FAIL(DEST_PS);
|
|
TX_STATUS_FAIL(HOST_ABORTED);
|
|
TX_STATUS_FAIL(BT_RETRY);
|
|
TX_STATUS_FAIL(STA_INVALID);
|
|
TX_STATUS_FAIL(FRAG_DROPPED);
|
|
TX_STATUS_FAIL(TID_DISABLE);
|
|
TX_STATUS_FAIL(FIFO_FLUSHED);
|
|
TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
|
|
TX_STATUS_FAIL(FW_DROP);
|
|
TX_STATUS_FAIL(STA_COLOR_MISMATCH_DROP);
|
|
}
|
|
|
|
return "UNKNOWN";
|
|
}
|
|
EXPORT_SYMBOL(iwl_get_tx_fail_reason);
|
|
#endif /* CONFIG_IWLWIFI_DEBUG */
|