This series for the OpenRISC architecture consists of mostly trivial fixups.
The most interesting bits of the series are:
* A fix to the timer code whereby the shortest trigger period is set to
100 cycles; previously, it was possible to set this to 1 cycle, but by
the time the register was written, that time had already passed and the
timer interrupt would not go off until the cycle counter had gone a full
cycle.
* Allowing a device tree binary to be passed in to the kernel from u-boot.
The OpenRISC architecture has been recently merged into upstream u-boot,
so this change gets OpenRISC Linux into sync with that project.
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Merge tag 'for-3.4' of git://openrisc.net/jonas/linux
Pull OpenRISC changes for 3.4 from Jonas Bonn:
"This series for the OpenRISC architecture consists of mostly trivial
fixups. The most interesting bits of the series are:
* A fix to the timer code whereby the shortest trigger period is set
to 100 cycles; previously, it was possible to set this to 1 cycle,
but by the time the register was written, that time had already
passed and the timer interrupt would not go off until the cycle
counter had gone a full cycle.
* Allowing a device tree binary to be passed in to the kernel from
u-boot. The OpenRISC architecture has been recently merged into
upstream u-boot, so this change gets OpenRISC Linux into sync with
that project."
* tag 'for-3.4' of git://openrisc.net/jonas/linux:
OpenRISC: Remove memory_start/end prototypes
openrisc: remove semicolon from KSTK_ defs
openrisc: sanitize use of orig_gpr11
openrisc: fix virt_addr_valid
OpenRISC: Export dump_stack()
OpenRISC: Select GENERIC_ATOMIC64
openrisc: Set shortest clock event to 100 ticks
openrisc: included linux/thread_info.h twice
OpenRISC: Use set_current_blocked() and block_sigmask()
OpenRISC: Don't mask signals if we fail to setup signal stack
OpenRISC: No need to reset handler if SA_ONESHOT
OpenRISC: Don't reimplement force_sigsegv()
openrisc: enable passing of flattened device tree pointer
arch/openrisc/mm/init.c: trivial: use BUG_ON
bab2d8c602