917 lines
23 KiB
C
917 lines
23 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/mach/flash.h>
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#include <mach/mxc_nand.h>
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#include <mach/hardware.h>
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#define DRIVER_NAME "mxc_nand"
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#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
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#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
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/* Addresses for NFC registers */
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#define NFC_BUF_SIZE 0x00
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#define NFC_BUF_ADDR 0x04
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#define NFC_FLASH_ADDR 0x06
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#define NFC_FLASH_CMD 0x08
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#define NFC_CONFIG 0x0a
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#define NFC_ECC_STATUS_RESULT 0x0c
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#define NFC_RSLTMAIN_AREA 0x0e
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#define NFC_RSLTSPARE_AREA 0x10
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#define NFC_WRPROT 0x12
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#define NFC_V1_UNLOCKSTART_BLKADDR 0x14
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#define NFC_V1_UNLOCKEND_BLKADDR 0x16
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#define NFC_V21_UNLOCKSTART_BLKADDR 0x20
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#define NFC_V21_UNLOCKEND_BLKADDR 0x22
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#define NFC_NF_WRPRST 0x18
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#define NFC_CONFIG1 0x1a
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#define NFC_CONFIG2 0x1c
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/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
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* for Command operation */
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#define NFC_CMD 0x1
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/* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
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* for Address operation */
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#define NFC_ADDR 0x2
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/* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
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* for Input operation */
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#define NFC_INPUT 0x4
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/* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
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* for Data Output operation */
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#define NFC_OUTPUT 0x8
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/* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
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* for Read ID operation */
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#define NFC_ID 0x10
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/* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
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* for Read Status operation */
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#define NFC_STATUS 0x20
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/* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
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* Status operation */
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#define NFC_INT 0x8000
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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#define NFC_BIG (1 << 5)
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#define NFC_RST (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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struct mxc_nand_host {
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struct mtd_info mtd;
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struct nand_chip nand;
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struct mtd_partition *parts;
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struct device *dev;
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void *spare0;
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void *main_area0;
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void __iomem *base;
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void __iomem *regs;
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int status_request;
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struct clk *clk;
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int clk_act;
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int irq;
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wait_queue_head_t irq_waitq;
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uint8_t *data_buf;
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unsigned int buf_start;
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int spare_len;
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void (*preset)(struct mtd_info *);
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void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
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void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
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void (*send_page)(struct mtd_info *, unsigned int);
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void (*send_read_id)(struct mxc_nand_host *);
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uint16_t (*get_dev_status)(struct mxc_nand_host *);
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int (*check_int)(struct mxc_nand_host *);
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};
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/* OOB placement block for use with hardware ecc generation */
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static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
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.eccbytes = 5,
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.eccpos = {6, 7, 8, 9, 10},
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.oobfree = {{0, 5}, {12, 4}, }
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};
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static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
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.eccbytes = 20,
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.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
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38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
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.oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
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};
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/* OOB description for 512 byte pages with 16 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
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.eccbytes = 1 * 9,
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.eccpos = {
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7, 8, 9, 10, 11, 12, 13, 14, 15
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},
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.oobfree = {
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{.offset = 0, .length = 5}
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}
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};
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/* OOB description for 2048 byte pages with 64 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
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.eccbytes = 4 * 9,
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.eccpos = {
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7, 8, 9, 10, 11, 12, 13, 14, 15,
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23, 24, 25, 26, 27, 28, 29, 30, 31,
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39, 40, 41, 42, 43, 44, 45, 46, 47,
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55, 56, 57, 58, 59, 60, 61, 62, 63
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},
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.oobfree = {
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{.offset = 2, .length = 4},
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{.offset = 16, .length = 7},
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{.offset = 32, .length = 7},
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{.offset = 48, .length = 7}
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}
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};
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#ifdef CONFIG_MTD_PARTITIONS
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static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
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#endif
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static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
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{
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struct mxc_nand_host *host = dev_id;
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disable_irq_nosync(irq);
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wake_up(&host->irq_waitq);
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return IRQ_HANDLED;
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}
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static int check_int_v1_v2(struct mxc_nand_host *host)
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{
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uint32_t tmp;
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tmp = readw(host->regs + NFC_CONFIG2);
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if (!(tmp & NFC_INT))
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return 0;
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writew(tmp & ~NFC_INT, NFC_CONFIG2);
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return 1;
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}
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/* This function polls the NANDFC to wait for the basic operation to
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* complete by checking the INT bit of config2 register.
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*/
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static void wait_op_done(struct mxc_nand_host *host, int useirq)
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{
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int max_retries = 8000;
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if (useirq) {
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if (!host->check_int(host)) {
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enable_irq(host->irq);
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wait_event(host->irq_waitq, host->check_int(host));
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}
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} else {
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while (max_retries-- > 0) {
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if (host->check_int(host))
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break;
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udelay(1);
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}
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if (max_retries < 0)
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DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
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__func__);
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}
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}
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/* This function issues the specified command to the NAND device and
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* waits for completion. */
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static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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{
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DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
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writew(cmd, host->regs + NFC_FLASH_CMD);
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writew(NFC_CMD, host->regs + NFC_CONFIG2);
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if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
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int max_retries = 100;
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/* Reset completion is indicated by NFC_CONFIG2 */
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/* being set to 0 */
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while (max_retries-- > 0) {
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if (readw(host->regs + NFC_CONFIG2) == 0) {
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break;
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}
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udelay(1);
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}
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if (max_retries < 0)
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DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
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__func__);
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} else {
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/* Wait for operation to complete */
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wait_op_done(host, useirq);
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}
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}
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/* This function sends an address (or partial address) to the
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* NAND device. The address is used to select the source/destination for
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* a NAND command. */
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static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
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{
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DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
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writew(addr, host->regs + NFC_FLASH_ADDR);
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writew(NFC_ADDR, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, islast);
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}
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static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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int bufs, i;
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if (nfc_is_v1() && mtd->writesize > 512)
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bufs = 4;
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else
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bufs = 1;
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for (i = 0; i < bufs; i++) {
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/* NANDFC buffer 0 is used for page read/write */
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writew(i, host->regs + NFC_BUF_ADDR);
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writew(ops, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, true);
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}
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}
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/* Request the NANDFC to perform a read of the NAND device ID. */
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static void send_read_id_v1_v2(struct mxc_nand_host *host)
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{
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struct nand_chip *this = &host->nand;
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/* NANDFC buffer 0 is used for device ID output */
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writew(0x0, host->regs + NFC_BUF_ADDR);
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writew(NFC_ID, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, true);
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if (this->options & NAND_BUSWIDTH_16) {
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void __iomem *main_buf = host->main_area0;
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/* compress the ID info */
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writeb(readb(main_buf + 2), main_buf + 1);
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writeb(readb(main_buf + 4), main_buf + 2);
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writeb(readb(main_buf + 6), main_buf + 3);
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writeb(readb(main_buf + 8), main_buf + 4);
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writeb(readb(main_buf + 10), main_buf + 5);
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}
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memcpy(host->data_buf, host->main_area0, 16);
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}
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/* This function requests the NANDFC to perform a read of the
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* NAND device status and returns the current status. */
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static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
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{
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void __iomem *main_buf = host->main_area0;
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uint32_t store;
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uint16_t ret;
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writew(0x0, NFC_V1_V2_BUF_ADDR);
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/*
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* The device status is stored in main_area0. To
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* prevent corruption of the buffer save the value
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* and restore it afterwards.
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*/
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store = readl(main_buf);
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writew(NFC_STATUS, host->regs + NFC_CONFIG2);
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wait_op_done(host, true);
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ret = readw(main_buf);
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writel(store, main_buf);
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return ret;
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}
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/* This functions is used by upper layer to checks if device is ready */
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static int mxc_nand_dev_ready(struct mtd_info *mtd)
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{
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/*
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* NFC handles R/B internally. Therefore, this function
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* always returns status as ready.
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*/
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return 1;
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}
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static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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/*
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* If HW ECC is enabled, we turn it on during init. There is
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* no need to enable again here.
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*/
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}
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static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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/*
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* 1-Bit errors are automatically corrected in HW. No need for
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* additional correction. 2-Bit errors cannot be corrected by
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* HW ECC, so we need to return failure
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*/
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uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
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if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
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DEBUG(MTD_DEBUG_LEVEL0,
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"MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
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return -1;
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}
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return 0;
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}
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static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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return 0;
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}
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static u_char mxc_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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uint8_t ret;
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/* Check for status request */
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if (host->status_request)
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return host->get_dev_status(host) & 0xFF;
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ret = *(uint8_t *)(host->data_buf + host->buf_start);
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host->buf_start++;
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return ret;
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}
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static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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uint16_t ret;
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ret = *(uint16_t *)(host->data_buf + host->buf_start);
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host->buf_start += 2;
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return ret;
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}
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/* Write data of length len to buffer buf. The data to be
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* written on NAND Flash is first copied to RAMbuffer. After the Data Input
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* Operation by the NFC, the data is written to NAND Flash */
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static void mxc_nand_write_buf(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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u16 col = host->buf_start;
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int n = mtd->oobsize + mtd->writesize - col;
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n = min(n, len);
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memcpy(host->data_buf + col, buf, n);
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host->buf_start += n;
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}
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/* Read the data buffer from the NAND Flash. To read the data from NAND
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* Flash first the data output cycle is initiated by the NFC, which copies
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* the data to RAMbuffer. This data of length len is then copied to buffer buf.
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*/
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static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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u16 col = host->buf_start;
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int n = mtd->oobsize + mtd->writesize - col;
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n = min(n, len);
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memcpy(buf, host->data_buf + col, len);
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host->buf_start += len;
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}
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/* Used by the upper layer to verify the data in NAND Flash
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* with the data in the buf. */
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static int mxc_nand_verify_buf(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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return -EFAULT;
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}
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/* This function is used by upper layer for select and
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* deselect of the NAND chip */
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static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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switch (chip) {
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case -1:
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/* Disable the NFC clock */
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if (host->clk_act) {
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clk_disable(host->clk);
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host->clk_act = 0;
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}
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break;
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case 0:
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/* Enable the NFC clock */
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if (!host->clk_act) {
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clk_enable(host->clk);
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host->clk_act = 1;
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}
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break;
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default:
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break;
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}
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}
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/*
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* Function to transfer data to/from spare area.
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*/
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static void copy_spare(struct mtd_info *mtd, bool bfrom)
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{
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struct nand_chip *this = mtd->priv;
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struct mxc_nand_host *host = this->priv;
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u16 i, j;
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u16 n = mtd->writesize >> 9;
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u8 *d = host->data_buf + mtd->writesize;
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u8 *s = host->spare0;
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u16 t = host->spare_len;
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|
j = (mtd->oobsize / n >> 1) << 1;
|
|
|
|
if (bfrom) {
|
|
for (i = 0; i < n - 1; i++)
|
|
memcpy(d + i * j, s + i * t, j);
|
|
|
|
/* the last section */
|
|
memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
|
|
} else {
|
|
for (i = 0; i < n - 1; i++)
|
|
memcpy(&s[i * t], &d[i * j], j);
|
|
|
|
/* the last section */
|
|
memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
|
|
}
|
|
}
|
|
|
|
static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct mxc_nand_host *host = nand_chip->priv;
|
|
|
|
/* Write out column address, if necessary */
|
|
if (column != -1) {
|
|
/*
|
|
* MXC NANDFC can only perform full page+spare or
|
|
* spare-only read/write. When the upper layers
|
|
* layers perform a read/write buf operation,
|
|
* we will used the saved column address to index into
|
|
* the full page.
|
|
*/
|
|
host->send_addr(host, 0, page_addr == -1);
|
|
if (mtd->writesize > 512)
|
|
/* another col addr cycle for 2k page */
|
|
host->send_addr(host, 0, false);
|
|
}
|
|
|
|
/* Write out page address, if necessary */
|
|
if (page_addr != -1) {
|
|
/* paddr_0 - p_addr_7 */
|
|
host->send_addr(host, (page_addr & 0xff), false);
|
|
|
|
if (mtd->writesize > 512) {
|
|
if (mtd->size >= 0x10000000) {
|
|
/* paddr_8 - paddr_15 */
|
|
host->send_addr(host, (page_addr >> 8) & 0xff, false);
|
|
host->send_addr(host, (page_addr >> 16) & 0xff, true);
|
|
} else
|
|
/* paddr_8 - paddr_15 */
|
|
host->send_addr(host, (page_addr >> 8) & 0xff, true);
|
|
} else {
|
|
/* One more address cycle for higher density devices */
|
|
if (mtd->size >= 0x4000000) {
|
|
/* paddr_8 - paddr_15 */
|
|
host->send_addr(host, (page_addr >> 8) & 0xff, false);
|
|
host->send_addr(host, (page_addr >> 16) & 0xff, true);
|
|
} else
|
|
/* paddr_8 - paddr_15 */
|
|
host->send_addr(host, (page_addr >> 8) & 0xff, true);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void preset_v1_v2(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct mxc_nand_host *host = nand_chip->priv;
|
|
uint16_t tmp;
|
|
|
|
/* enable interrupt, disable spare enable */
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
tmp &= ~NFC_INT_MSK;
|
|
tmp &= ~NFC_SP_EN;
|
|
if (nand_chip->ecc.mode == NAND_ECC_HW) {
|
|
tmp |= NFC_ECC_EN;
|
|
} else {
|
|
tmp &= ~NFC_ECC_EN;
|
|
}
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
/* preset operation */
|
|
|
|
/* Unlock the internal RAM Buffer */
|
|
writew(0x2, host->regs + NFC_CONFIG);
|
|
|
|
/* Blocks to be unlocked */
|
|
if (nfc_is_v21()) {
|
|
writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
|
|
writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
|
|
} else if (nfc_is_v1()) {
|
|
writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
|
|
writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
|
|
} else
|
|
BUG();
|
|
|
|
/* Unlock Block Command for given address range */
|
|
writew(0x4, host->regs + NFC_WRPROT);
|
|
}
|
|
|
|
/* Used by the upper layer to write command to NAND Flash for
|
|
* different operations to be carried out on NAND Flash */
|
|
static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|
int column, int page_addr)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct mxc_nand_host *host = nand_chip->priv;
|
|
|
|
DEBUG(MTD_DEBUG_LEVEL3,
|
|
"mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
|
|
command, column, page_addr);
|
|
|
|
/* Reset command state information */
|
|
host->status_request = false;
|
|
|
|
/* Command pre-processing step */
|
|
switch (command) {
|
|
case NAND_CMD_RESET:
|
|
host->preset(mtd);
|
|
host->send_cmd(host, command, false);
|
|
break;
|
|
|
|
case NAND_CMD_STATUS:
|
|
host->buf_start = 0;
|
|
host->status_request = true;
|
|
|
|
host->send_cmd(host, command, true);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
break;
|
|
|
|
case NAND_CMD_READ0:
|
|
case NAND_CMD_READOOB:
|
|
if (command == NAND_CMD_READ0)
|
|
host->buf_start = column;
|
|
else
|
|
host->buf_start = column + mtd->writesize;
|
|
|
|
command = NAND_CMD_READ0; /* only READ0 is valid */
|
|
|
|
host->send_cmd(host, command, false);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
|
|
if (mtd->writesize > 512)
|
|
host->send_cmd(host, NAND_CMD_READSTART, true);
|
|
|
|
host->send_page(mtd, NFC_OUTPUT);
|
|
|
|
memcpy(host->data_buf, host->main_area0, mtd->writesize);
|
|
copy_spare(mtd, true);
|
|
break;
|
|
|
|
case NAND_CMD_SEQIN:
|
|
if (column >= mtd->writesize)
|
|
/* call ourself to read a page */
|
|
mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
|
|
|
|
host->buf_start = column;
|
|
|
|
host->send_cmd(host, command, false);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
break;
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
memcpy(host->main_area0, host->data_buf, mtd->writesize);
|
|
copy_spare(mtd, false);
|
|
host->send_page(mtd, NFC_INPUT);
|
|
host->send_cmd(host, command, true);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
break;
|
|
|
|
case NAND_CMD_READID:
|
|
host->send_cmd(host, command, true);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
host->send_read_id(host);
|
|
host->buf_start = column;
|
|
break;
|
|
|
|
case NAND_CMD_ERASE1:
|
|
case NAND_CMD_ERASE2:
|
|
host->send_cmd(host, command, false);
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The generic flash bbt decriptors overlap with our ecc
|
|
* hardware, so define some i.MX specific ones.
|
|
*/
|
|
static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
|
|
static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
|
|
|
|
static struct nand_bbt_descr bbt_main_descr = {
|
|
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
|
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
|
|
.offs = 0,
|
|
.len = 4,
|
|
.veroffs = 4,
|
|
.maxblocks = 4,
|
|
.pattern = bbt_pattern,
|
|
};
|
|
|
|
static struct nand_bbt_descr bbt_mirror_descr = {
|
|
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
|
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
|
|
.offs = 0,
|
|
.len = 4,
|
|
.veroffs = 4,
|
|
.maxblocks = 4,
|
|
.pattern = mirror_pattern,
|
|
};
|
|
|
|
static int __init mxcnd_probe(struct platform_device *pdev)
|
|
{
|
|
struct nand_chip *this;
|
|
struct mtd_info *mtd;
|
|
struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
|
|
struct mxc_nand_host *host;
|
|
struct resource *res;
|
|
int err = 0, nr_parts = 0;
|
|
struct nand_ecclayout *oob_smallpage, *oob_largepage;
|
|
|
|
/* Allocate memory for MTD device structure and private data */
|
|
host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
|
|
NAND_MAX_OOBSIZE, GFP_KERNEL);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
host->data_buf = (uint8_t *)(host + 1);
|
|
|
|
host->dev = &pdev->dev;
|
|
/* structures must be linked */
|
|
this = &host->nand;
|
|
mtd = &host->mtd;
|
|
mtd->priv = this;
|
|
mtd->owner = THIS_MODULE;
|
|
mtd->dev.parent = &pdev->dev;
|
|
mtd->name = DRIVER_NAME;
|
|
|
|
/* 50 us command delay time */
|
|
this->chip_delay = 5;
|
|
|
|
this->priv = host;
|
|
this->dev_ready = mxc_nand_dev_ready;
|
|
this->cmdfunc = mxc_nand_command;
|
|
this->select_chip = mxc_nand_select_chip;
|
|
this->read_byte = mxc_nand_read_byte;
|
|
this->read_word = mxc_nand_read_word;
|
|
this->write_buf = mxc_nand_write_buf;
|
|
this->read_buf = mxc_nand_read_buf;
|
|
this->verify_buf = mxc_nand_verify_buf;
|
|
|
|
host->clk = clk_get(&pdev->dev, "nfc");
|
|
if (IS_ERR(host->clk)) {
|
|
err = PTR_ERR(host->clk);
|
|
goto eclk;
|
|
}
|
|
|
|
clk_enable(host->clk);
|
|
host->clk_act = 1;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
err = -ENODEV;
|
|
goto eres;
|
|
}
|
|
|
|
host->base = ioremap(res->start, resource_size(res));
|
|
if (!host->base) {
|
|
err = -ENOMEM;
|
|
goto eres;
|
|
}
|
|
|
|
host->main_area0 = host->base;
|
|
|
|
if (nfc_is_v1() || nfc_is_v21()) {
|
|
host->preset = preset_v1_v2;
|
|
host->send_cmd = send_cmd_v1_v2;
|
|
host->send_addr = send_addr_v1_v2;
|
|
host->send_page = send_page_v1_v2;
|
|
host->send_read_id = send_read_id_v1_v2;
|
|
host->get_dev_status = get_dev_status_v1_v2;
|
|
host->check_int = check_int_v1_v2;
|
|
}
|
|
|
|
if (nfc_is_v21()) {
|
|
host->regs = host->base + 0x1e00;
|
|
host->spare0 = host->base + 0x1000;
|
|
host->spare_len = 64;
|
|
oob_smallpage = &nandv2_hw_eccoob_smallpage;
|
|
oob_largepage = &nandv2_hw_eccoob_largepage;
|
|
this->ecc.bytes = 9;
|
|
} else if (nfc_is_v1()) {
|
|
host->regs = host->base + 0xe00;
|
|
host->spare0 = host->base + 0x800;
|
|
host->spare_len = 16;
|
|
oob_smallpage = &nandv1_hw_eccoob_smallpage;
|
|
oob_largepage = &nandv1_hw_eccoob_largepage;
|
|
this->ecc.bytes = 3;
|
|
} else
|
|
BUG();
|
|
|
|
this->ecc.size = 512;
|
|
this->ecc.layout = oob_smallpage;
|
|
|
|
if (pdata->hw_ecc) {
|
|
this->ecc.calculate = mxc_nand_calculate_ecc;
|
|
this->ecc.hwctl = mxc_nand_enable_hwecc;
|
|
this->ecc.correct = mxc_nand_correct_data;
|
|
this->ecc.mode = NAND_ECC_HW;
|
|
} else {
|
|
this->ecc.mode = NAND_ECC_SOFT;
|
|
}
|
|
|
|
/* NAND bus width determines access funtions used by upper layer */
|
|
if (pdata->width == 2)
|
|
this->options |= NAND_BUSWIDTH_16;
|
|
|
|
if (pdata->flash_bbt) {
|
|
this->bbt_td = &bbt_main_descr;
|
|
this->bbt_md = &bbt_mirror_descr;
|
|
/* update flash based bbt */
|
|
this->options |= NAND_USE_FLASH_BBT;
|
|
}
|
|
|
|
init_waitqueue_head(&host->irq_waitq);
|
|
|
|
host->irq = platform_get_irq(pdev, 0);
|
|
|
|
err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
|
|
if (err)
|
|
goto eirq;
|
|
|
|
/* first scan to find the device and get the page size */
|
|
if (nand_scan_ident(mtd, 1, NULL)) {
|
|
err = -ENXIO;
|
|
goto escan;
|
|
}
|
|
|
|
if (mtd->writesize == 2048)
|
|
this->ecc.layout = oob_largepage;
|
|
|
|
/* second phase scan */
|
|
if (nand_scan_tail(mtd)) {
|
|
err = -ENXIO;
|
|
goto escan;
|
|
}
|
|
|
|
/* Register the partitions */
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
nr_parts =
|
|
parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
|
|
if (nr_parts > 0)
|
|
add_mtd_partitions(mtd, host->parts, nr_parts);
|
|
else
|
|
#endif
|
|
{
|
|
pr_info("Registering %s as whole device\n", mtd->name);
|
|
add_mtd_device(mtd);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
return 0;
|
|
|
|
escan:
|
|
free_irq(host->irq, host);
|
|
eirq:
|
|
iounmap(host->base);
|
|
eres:
|
|
clk_put(host->clk);
|
|
eclk:
|
|
kfree(host);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int __devexit mxcnd_remove(struct platform_device *pdev)
|
|
{
|
|
struct mxc_nand_host *host = platform_get_drvdata(pdev);
|
|
|
|
clk_put(host->clk);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
nand_release(&host->mtd);
|
|
free_irq(host->irq, host);
|
|
iounmap(host->base);
|
|
kfree(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mxcnd_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
.remove = __devexit_p(mxcnd_remove),
|
|
};
|
|
|
|
static int __init mxc_nd_init(void)
|
|
{
|
|
return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
|
|
}
|
|
|
|
static void __exit mxc_nd_cleanup(void)
|
|
{
|
|
/* Unregister the device structure */
|
|
platform_driver_unregister(&mxcnd_driver);
|
|
}
|
|
|
|
module_init(mxc_nd_init);
|
|
module_exit(mxc_nd_cleanup);
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
MODULE_DESCRIPTION("MXC NAND MTD driver");
|
|
MODULE_LICENSE("GPL");
|