693 lines
16 KiB
C
693 lines
16 KiB
C
/*
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* Kernel-based Virtual Machine driver for Linux
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*
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* This module enables machines with Intel VT-x extensions to run virtual
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* machines without emulation or binary translation.
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*
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* MMU support
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*
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* Copyright (C) 2006 Qumranet, Inc.
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*
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* Authors:
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* Yaniv Kamay <yaniv@qumranet.com>
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* Avi Kivity <avi@qumranet.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <asm/page.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include "vmx.h"
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#include "kvm.h"
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#define pgprintk(x...) do { } while (0)
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#define ASSERT(x) \
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if (!(x)) { \
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printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
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__FILE__, __LINE__, #x); \
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}
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#define PT64_ENT_PER_PAGE 512
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#define PT32_ENT_PER_PAGE 1024
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#define PT_WRITABLE_SHIFT 1
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#define PT_PRESENT_MASK (1ULL << 0)
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#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
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#define PT_USER_MASK (1ULL << 2)
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#define PT_PWT_MASK (1ULL << 3)
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#define PT_PCD_MASK (1ULL << 4)
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#define PT_ACCESSED_MASK (1ULL << 5)
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#define PT_DIRTY_MASK (1ULL << 6)
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#define PT_PAGE_SIZE_MASK (1ULL << 7)
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#define PT_PAT_MASK (1ULL << 7)
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#define PT_GLOBAL_MASK (1ULL << 8)
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#define PT64_NX_MASK (1ULL << 63)
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#define PT_PAT_SHIFT 7
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#define PT_DIR_PAT_SHIFT 12
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#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
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#define PT32_DIR_PSE36_SIZE 4
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#define PT32_DIR_PSE36_SHIFT 13
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#define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
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#define PT32_PTE_COPY_MASK \
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(PT_PRESENT_MASK | PT_ACCESSED_MASK | PT_DIRTY_MASK | PT_GLOBAL_MASK)
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#define PT64_PTE_COPY_MASK (PT64_NX_MASK | PT32_PTE_COPY_MASK)
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#define PT_FIRST_AVAIL_BITS_SHIFT 9
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#define PT64_SECOND_AVAIL_BITS_SHIFT 52
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#define PT_SHADOW_PS_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
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#define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
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#define PT_SHADOW_WRITABLE_SHIFT (PT_FIRST_AVAIL_BITS_SHIFT + 1)
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#define PT_SHADOW_WRITABLE_MASK (1ULL << PT_SHADOW_WRITABLE_SHIFT)
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#define PT_SHADOW_USER_SHIFT (PT_SHADOW_WRITABLE_SHIFT + 1)
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#define PT_SHADOW_USER_MASK (1ULL << (PT_SHADOW_USER_SHIFT))
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#define PT_SHADOW_BITS_OFFSET (PT_SHADOW_WRITABLE_SHIFT - PT_WRITABLE_SHIFT)
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#define VALID_PAGE(x) ((x) != INVALID_PAGE)
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#define PT64_LEVEL_BITS 9
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#define PT64_LEVEL_SHIFT(level) \
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( PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS )
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#define PT64_LEVEL_MASK(level) \
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(((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
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#define PT64_INDEX(address, level)\
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(((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
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#define PT32_LEVEL_BITS 10
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#define PT32_LEVEL_SHIFT(level) \
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( PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS )
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#define PT32_LEVEL_MASK(level) \
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(((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
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#define PT32_INDEX(address, level)\
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(((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
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#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & PAGE_MASK)
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#define PT64_DIR_BASE_ADDR_MASK \
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(PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
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#define PT32_BASE_ADDR_MASK PAGE_MASK
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#define PT32_DIR_BASE_ADDR_MASK \
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(PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
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#define PFERR_PRESENT_MASK (1U << 0)
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#define PFERR_WRITE_MASK (1U << 1)
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#define PFERR_USER_MASK (1U << 2)
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#define PT64_ROOT_LEVEL 4
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#define PT32_ROOT_LEVEL 2
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#define PT32E_ROOT_LEVEL 3
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#define PT_DIRECTORY_LEVEL 2
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#define PT_PAGE_TABLE_LEVEL 1
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static int is_write_protection(struct kvm_vcpu *vcpu)
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{
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return vcpu->cr0 & CR0_WP_MASK;
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}
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static int is_cpuid_PSE36(void)
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{
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return 1;
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}
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static int is_present_pte(unsigned long pte)
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{
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return pte & PT_PRESENT_MASK;
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}
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static int is_writeble_pte(unsigned long pte)
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{
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return pte & PT_WRITABLE_MASK;
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}
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static int is_io_pte(unsigned long pte)
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{
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return pte & PT_SHADOW_IO_MARK;
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}
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static void kvm_mmu_free_page(struct kvm_vcpu *vcpu, hpa_t page_hpa)
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{
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struct kvm_mmu_page *page_head = page_header(page_hpa);
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list_del(&page_head->link);
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page_head->page_hpa = page_hpa;
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list_add(&page_head->link, &vcpu->free_pages);
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}
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static int is_empty_shadow_page(hpa_t page_hpa)
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{
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u32 *pos;
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u32 *end;
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for (pos = __va(page_hpa), end = pos + PAGE_SIZE / sizeof(u32);
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pos != end; pos++)
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if (*pos != 0)
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return 0;
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return 1;
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}
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static hpa_t kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, u64 *parent_pte)
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{
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struct kvm_mmu_page *page;
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if (list_empty(&vcpu->free_pages))
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return INVALID_PAGE;
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page = list_entry(vcpu->free_pages.next, struct kvm_mmu_page, link);
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list_del(&page->link);
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list_add(&page->link, &vcpu->kvm->active_mmu_pages);
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ASSERT(is_empty_shadow_page(page->page_hpa));
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page->slot_bitmap = 0;
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page->global = 1;
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page->parent_pte = parent_pte;
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return page->page_hpa;
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}
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static void page_header_update_slot(struct kvm *kvm, void *pte, gpa_t gpa)
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{
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int slot = memslot_id(kvm, gfn_to_memslot(kvm, gpa >> PAGE_SHIFT));
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struct kvm_mmu_page *page_head = page_header(__pa(pte));
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__set_bit(slot, &page_head->slot_bitmap);
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}
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hpa_t safe_gpa_to_hpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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{
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hpa_t hpa = gpa_to_hpa(vcpu, gpa);
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return is_error_hpa(hpa) ? bad_page_address | (gpa & ~PAGE_MASK): hpa;
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}
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hpa_t gpa_to_hpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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{
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struct kvm_memory_slot *slot;
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struct page *page;
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ASSERT((gpa & HPA_ERR_MASK) == 0);
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slot = gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT);
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if (!slot)
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return gpa | HPA_ERR_MASK;
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page = gfn_to_page(slot, gpa >> PAGE_SHIFT);
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return ((hpa_t)page_to_pfn(page) << PAGE_SHIFT)
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| (gpa & (PAGE_SIZE-1));
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}
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hpa_t gva_to_hpa(struct kvm_vcpu *vcpu, gva_t gva)
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{
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gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
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if (gpa == UNMAPPED_GVA)
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return UNMAPPED_GVA;
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return gpa_to_hpa(vcpu, gpa);
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}
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static void release_pt_page_64(struct kvm_vcpu *vcpu, hpa_t page_hpa,
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int level)
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{
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ASSERT(vcpu);
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ASSERT(VALID_PAGE(page_hpa));
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ASSERT(level <= PT64_ROOT_LEVEL && level > 0);
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if (level == 1)
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memset(__va(page_hpa), 0, PAGE_SIZE);
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else {
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u64 *pos;
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u64 *end;
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for (pos = __va(page_hpa), end = pos + PT64_ENT_PER_PAGE;
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pos != end; pos++) {
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u64 current_ent = *pos;
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*pos = 0;
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if (is_present_pte(current_ent))
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release_pt_page_64(vcpu,
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current_ent &
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PT64_BASE_ADDR_MASK,
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level - 1);
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}
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}
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kvm_mmu_free_page(vcpu, page_hpa);
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}
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static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
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{
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}
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static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, hpa_t p)
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{
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int level = PT32E_ROOT_LEVEL;
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hpa_t table_addr = vcpu->mmu.root_hpa;
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for (; ; level--) {
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u32 index = PT64_INDEX(v, level);
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u64 *table;
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ASSERT(VALID_PAGE(table_addr));
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table = __va(table_addr);
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if (level == 1) {
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mark_page_dirty(vcpu->kvm, v >> PAGE_SHIFT);
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page_header_update_slot(vcpu->kvm, table, v);
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table[index] = p | PT_PRESENT_MASK | PT_WRITABLE_MASK |
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PT_USER_MASK;
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return 0;
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}
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if (table[index] == 0) {
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hpa_t new_table = kvm_mmu_alloc_page(vcpu,
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&table[index]);
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if (!VALID_PAGE(new_table)) {
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pgprintk("nonpaging_map: ENOMEM\n");
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return -ENOMEM;
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}
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if (level == PT32E_ROOT_LEVEL)
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table[index] = new_table | PT_PRESENT_MASK;
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else
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table[index] = new_table | PT_PRESENT_MASK |
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PT_WRITABLE_MASK | PT_USER_MASK;
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}
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table_addr = table[index] & PT64_BASE_ADDR_MASK;
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}
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}
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static void nonpaging_flush(struct kvm_vcpu *vcpu)
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{
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hpa_t root = vcpu->mmu.root_hpa;
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++kvm_stat.tlb_flush;
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pgprintk("nonpaging_flush\n");
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ASSERT(VALID_PAGE(root));
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release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
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root = kvm_mmu_alloc_page(vcpu, NULL);
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ASSERT(VALID_PAGE(root));
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vcpu->mmu.root_hpa = root;
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if (is_paging(vcpu))
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root |= (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK));
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kvm_arch_ops->set_cr3(vcpu, root);
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kvm_arch_ops->tlb_flush(vcpu);
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}
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static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
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{
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return vaddr;
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}
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static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
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u32 error_code)
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{
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int ret;
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gpa_t addr = gva;
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ASSERT(vcpu);
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ASSERT(VALID_PAGE(vcpu->mmu.root_hpa));
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for (;;) {
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hpa_t paddr;
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paddr = gpa_to_hpa(vcpu , addr & PT64_BASE_ADDR_MASK);
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if (is_error_hpa(paddr))
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return 1;
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ret = nonpaging_map(vcpu, addr & PAGE_MASK, paddr);
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if (ret) {
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nonpaging_flush(vcpu);
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continue;
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}
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break;
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}
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return ret;
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}
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static void nonpaging_inval_page(struct kvm_vcpu *vcpu, gva_t addr)
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{
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}
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static void nonpaging_free(struct kvm_vcpu *vcpu)
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{
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hpa_t root;
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ASSERT(vcpu);
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root = vcpu->mmu.root_hpa;
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if (VALID_PAGE(root))
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release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
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vcpu->mmu.root_hpa = INVALID_PAGE;
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}
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static int nonpaging_init_context(struct kvm_vcpu *vcpu)
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{
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struct kvm_mmu *context = &vcpu->mmu;
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context->new_cr3 = nonpaging_new_cr3;
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context->page_fault = nonpaging_page_fault;
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context->inval_page = nonpaging_inval_page;
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context->gva_to_gpa = nonpaging_gva_to_gpa;
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context->free = nonpaging_free;
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context->root_level = PT32E_ROOT_LEVEL;
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context->shadow_root_level = PT32E_ROOT_LEVEL;
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context->root_hpa = kvm_mmu_alloc_page(vcpu, NULL);
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ASSERT(VALID_PAGE(context->root_hpa));
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kvm_arch_ops->set_cr3(vcpu, context->root_hpa);
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return 0;
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}
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static void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
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{
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struct kvm_mmu_page *page, *npage;
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list_for_each_entry_safe(page, npage, &vcpu->kvm->active_mmu_pages,
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link) {
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if (page->global)
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continue;
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if (!page->parent_pte)
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continue;
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*page->parent_pte = 0;
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release_pt_page_64(vcpu, page->page_hpa, 1);
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}
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++kvm_stat.tlb_flush;
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kvm_arch_ops->tlb_flush(vcpu);
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}
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static void paging_new_cr3(struct kvm_vcpu *vcpu)
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{
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kvm_mmu_flush_tlb(vcpu);
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}
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static void mark_pagetable_nonglobal(void *shadow_pte)
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{
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page_header(__pa(shadow_pte))->global = 0;
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}
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static inline void set_pte_common(struct kvm_vcpu *vcpu,
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u64 *shadow_pte,
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gpa_t gaddr,
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int dirty,
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u64 access_bits)
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{
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hpa_t paddr;
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*shadow_pte |= access_bits << PT_SHADOW_BITS_OFFSET;
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if (!dirty)
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access_bits &= ~PT_WRITABLE_MASK;
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if (access_bits & PT_WRITABLE_MASK)
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mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
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*shadow_pte |= access_bits;
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paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
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if (!(*shadow_pte & PT_GLOBAL_MASK))
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mark_pagetable_nonglobal(shadow_pte);
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if (is_error_hpa(paddr)) {
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*shadow_pte |= gaddr;
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*shadow_pte |= PT_SHADOW_IO_MARK;
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*shadow_pte &= ~PT_PRESENT_MASK;
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} else {
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*shadow_pte |= paddr;
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page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
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}
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}
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static void inject_page_fault(struct kvm_vcpu *vcpu,
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u64 addr,
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u32 err_code)
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{
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kvm_arch_ops->inject_page_fault(vcpu, addr, err_code);
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}
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static inline int fix_read_pf(u64 *shadow_ent)
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{
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if ((*shadow_ent & PT_SHADOW_USER_MASK) &&
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!(*shadow_ent & PT_USER_MASK)) {
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/*
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* If supervisor write protect is disabled, we shadow kernel
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* pages as user pages so we can trap the write access.
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*/
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*shadow_ent |= PT_USER_MASK;
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*shadow_ent &= ~PT_WRITABLE_MASK;
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return 1;
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}
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return 0;
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}
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static int may_access(u64 pte, int write, int user)
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{
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if (user && !(pte & PT_USER_MASK))
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return 0;
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if (write && !(pte & PT_WRITABLE_MASK))
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return 0;
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return 1;
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}
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/*
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* Remove a shadow pte.
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*/
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static void paging_inval_page(struct kvm_vcpu *vcpu, gva_t addr)
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{
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hpa_t page_addr = vcpu->mmu.root_hpa;
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int level = vcpu->mmu.shadow_root_level;
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++kvm_stat.invlpg;
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for (; ; level--) {
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u32 index = PT64_INDEX(addr, level);
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u64 *table = __va(page_addr);
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if (level == PT_PAGE_TABLE_LEVEL ) {
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table[index] = 0;
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return;
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}
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if (!is_present_pte(table[index]))
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return;
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page_addr = table[index] & PT64_BASE_ADDR_MASK;
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if (level == PT_DIRECTORY_LEVEL &&
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(table[index] & PT_SHADOW_PS_MARK)) {
|
|
table[index] = 0;
|
|
release_pt_page_64(vcpu, page_addr, PT_PAGE_TABLE_LEVEL);
|
|
|
|
kvm_arch_ops->tlb_flush(vcpu);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void paging_free(struct kvm_vcpu *vcpu)
|
|
{
|
|
nonpaging_free(vcpu);
|
|
}
|
|
|
|
#define PTTYPE 64
|
|
#include "paging_tmpl.h"
|
|
#undef PTTYPE
|
|
|
|
#define PTTYPE 32
|
|
#include "paging_tmpl.h"
|
|
#undef PTTYPE
|
|
|
|
static int paging64_init_context(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_mmu *context = &vcpu->mmu;
|
|
|
|
ASSERT(is_pae(vcpu));
|
|
context->new_cr3 = paging_new_cr3;
|
|
context->page_fault = paging64_page_fault;
|
|
context->inval_page = paging_inval_page;
|
|
context->gva_to_gpa = paging64_gva_to_gpa;
|
|
context->free = paging_free;
|
|
context->root_level = PT64_ROOT_LEVEL;
|
|
context->shadow_root_level = PT64_ROOT_LEVEL;
|
|
context->root_hpa = kvm_mmu_alloc_page(vcpu, NULL);
|
|
ASSERT(VALID_PAGE(context->root_hpa));
|
|
kvm_arch_ops->set_cr3(vcpu, context->root_hpa |
|
|
(vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
|
|
return 0;
|
|
}
|
|
|
|
static int paging32_init_context(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_mmu *context = &vcpu->mmu;
|
|
|
|
context->new_cr3 = paging_new_cr3;
|
|
context->page_fault = paging32_page_fault;
|
|
context->inval_page = paging_inval_page;
|
|
context->gva_to_gpa = paging32_gva_to_gpa;
|
|
context->free = paging_free;
|
|
context->root_level = PT32_ROOT_LEVEL;
|
|
context->shadow_root_level = PT32E_ROOT_LEVEL;
|
|
context->root_hpa = kvm_mmu_alloc_page(vcpu, NULL);
|
|
ASSERT(VALID_PAGE(context->root_hpa));
|
|
kvm_arch_ops->set_cr3(vcpu, context->root_hpa |
|
|
(vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
|
|
return 0;
|
|
}
|
|
|
|
static int paging32E_init_context(struct kvm_vcpu *vcpu)
|
|
{
|
|
int ret;
|
|
|
|
if ((ret = paging64_init_context(vcpu)))
|
|
return ret;
|
|
|
|
vcpu->mmu.root_level = PT32E_ROOT_LEVEL;
|
|
vcpu->mmu.shadow_root_level = PT32E_ROOT_LEVEL;
|
|
return 0;
|
|
}
|
|
|
|
static int init_kvm_mmu(struct kvm_vcpu *vcpu)
|
|
{
|
|
ASSERT(vcpu);
|
|
ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
|
|
|
|
if (!is_paging(vcpu))
|
|
return nonpaging_init_context(vcpu);
|
|
else if (kvm_arch_ops->is_long_mode(vcpu))
|
|
return paging64_init_context(vcpu);
|
|
else if (is_pae(vcpu))
|
|
return paging32E_init_context(vcpu);
|
|
else
|
|
return paging32_init_context(vcpu);
|
|
}
|
|
|
|
static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
|
|
{
|
|
ASSERT(vcpu);
|
|
if (VALID_PAGE(vcpu->mmu.root_hpa)) {
|
|
vcpu->mmu.free(vcpu);
|
|
vcpu->mmu.root_hpa = INVALID_PAGE;
|
|
}
|
|
}
|
|
|
|
int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
|
|
{
|
|
destroy_kvm_mmu(vcpu);
|
|
return init_kvm_mmu(vcpu);
|
|
}
|
|
|
|
static void free_mmu_pages(struct kvm_vcpu *vcpu)
|
|
{
|
|
while (!list_empty(&vcpu->free_pages)) {
|
|
struct kvm_mmu_page *page;
|
|
|
|
page = list_entry(vcpu->free_pages.next,
|
|
struct kvm_mmu_page, link);
|
|
list_del(&page->link);
|
|
__free_page(pfn_to_page(page->page_hpa >> PAGE_SHIFT));
|
|
page->page_hpa = INVALID_PAGE;
|
|
}
|
|
}
|
|
|
|
static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
|
|
{
|
|
int i;
|
|
|
|
ASSERT(vcpu);
|
|
|
|
for (i = 0; i < KVM_NUM_MMU_PAGES; i++) {
|
|
struct page *page;
|
|
struct kvm_mmu_page *page_header = &vcpu->page_header_buf[i];
|
|
|
|
INIT_LIST_HEAD(&page_header->link);
|
|
if ((page = alloc_page(GFP_KVM_MMU)) == NULL)
|
|
goto error_1;
|
|
page->private = (unsigned long)page_header;
|
|
page_header->page_hpa = (hpa_t)page_to_pfn(page) << PAGE_SHIFT;
|
|
memset(__va(page_header->page_hpa), 0, PAGE_SIZE);
|
|
list_add(&page_header->link, &vcpu->free_pages);
|
|
}
|
|
return 0;
|
|
|
|
error_1:
|
|
free_mmu_pages(vcpu);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
int kvm_mmu_init(struct kvm_vcpu *vcpu)
|
|
{
|
|
int r;
|
|
|
|
ASSERT(vcpu);
|
|
ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
|
|
ASSERT(list_empty(&vcpu->free_pages));
|
|
|
|
r = alloc_mmu_pages(vcpu);
|
|
if (r)
|
|
goto out;
|
|
|
|
r = init_kvm_mmu(vcpu);
|
|
if (r)
|
|
goto out_free_pages;
|
|
|
|
return 0;
|
|
|
|
out_free_pages:
|
|
free_mmu_pages(vcpu);
|
|
out:
|
|
return r;
|
|
}
|
|
|
|
void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
|
|
{
|
|
ASSERT(vcpu);
|
|
|
|
destroy_kvm_mmu(vcpu);
|
|
free_mmu_pages(vcpu);
|
|
}
|
|
|
|
void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
|
|
{
|
|
struct kvm_mmu_page *page;
|
|
|
|
list_for_each_entry(page, &kvm->active_mmu_pages, link) {
|
|
int i;
|
|
u64 *pt;
|
|
|
|
if (!test_bit(slot, &page->slot_bitmap))
|
|
continue;
|
|
|
|
pt = __va(page->page_hpa);
|
|
for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
|
|
/* avoid RMW */
|
|
if (pt[i] & PT_WRITABLE_MASK)
|
|
pt[i] &= ~PT_WRITABLE_MASK;
|
|
|
|
}
|
|
}
|