657ebfadc1
clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
72 lines
2 KiB
C
72 lines
2 KiB
C
/*
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* OMAP36xx-specific clkops
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Mike Turquette
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* Vijaykumar GN
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* Paul Walmsley
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
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* Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock36xx.h"
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/**
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* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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* from HSDivider PWRDN problem Implements Errata ID: i556.
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* @clk: DPLL output struct clk
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*
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* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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* valueafter their respective PWRDN bits are set. Any dummy write
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* (Any other value different from the Read value) to the
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* corresponding CM_CLKSEL register will refresh the dividers.
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*/
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static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
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{
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u32 dummy_v, orig_v, clksel_shift;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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/* Restore the dividers */
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if (!ret) {
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clksel_shift = __ffs(clk->parent->clksel_mask);
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orig_v = __raw_readl(clk->parent->clksel_reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << clksel_shift);
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__raw_writel(dummy_v, clk->parent->clksel_reg);
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/* Write the original divider */
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__raw_writel(orig_v, clk->parent->clksel_reg);
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}
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return ret;
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}
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const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
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.enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
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.disable = omap2_dflt_clk_disable,
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.find_companion = omap2_clk_dflt_find_companion,
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.find_idlest = omap2_clk_dflt_find_idlest,
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};
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