af39bb8b07
This adds the basic infrastructure used by all of the different Coldfire CPUs. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
238 lines
6.8 KiB
C
238 lines
6.8 KiB
C
/*
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* Coldfire generic GPIO support
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*
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* (C) Copyright 2009, Steven King <sfking@fdwdc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef coldfire_gpio_h
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#define coldfire_gpio_h
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#include <linux/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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/*
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* The Freescale Coldfire family is quite varied in how they implement GPIO.
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* Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
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* only one port, others have multiple ports; some have a single data latch
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* for both input and output, others have a separate pin data register to read
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* input; some require a read-modify-write access to change an output, others
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* have set and clear registers for some of the outputs; Some have all the
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* GPIOs in a single control area, others have some GPIOs implemented in
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* different modules.
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*
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* This implementation attempts accomodate the differences while presenting
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* a generic interface that will optimize to as few instructions as possible.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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/* These parts have GPIO organized by 8 bit ports */
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#define MCFGPIO_PORTTYPE u8
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#define MCFGPIO_PORTSIZE 8
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#define mcfgpio_read(port) __raw_readb(port)
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#define mcfgpio_write(data, port) __raw_writeb(data, port)
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#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
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/* These parts have GPIO organized by 16 bit ports */
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#define MCFGPIO_PORTTYPE u16
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#define MCFGPIO_PORTSIZE 16
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#define mcfgpio_read(port) __raw_readw(port)
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#define mcfgpio_write(data, port) __raw_writew(data, port)
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#elif defined(CONFIG_M5249)
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/* These parts have GPIO organized by 32 bit ports */
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#define MCFGPIO_PORTTYPE u32
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#define MCFGPIO_PORTSIZE 32
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#define mcfgpio_read(port) __raw_readl(port)
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#define mcfgpio_write(data, port) __raw_writel(data, port)
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#endif
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#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
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#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
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#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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/*
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* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
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* read-modify-write to change an output and a GPIO module which has separate
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* set/clr registers to directly change outputs with a single write access.
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*/
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#if defined(CONFIG_M528x)
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/*
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* The 528x also has GPIOs in other modules (GPT, QADC) which use
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* read-modify-write as well as those controlled by the EPORT and GPIO modules.
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*/
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#define MCFGPIO_SCR_START 40
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#else
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#define MCFGPIO_SCR_START 8
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#endif
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#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#else
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#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
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/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
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#define MCFGPIO_SETR_PORT(gpio) 0
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#define MCFGPIO_CLRR_PORT(gpio) 0
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#endif
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/*
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* Coldfire specific helper functions
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*/
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/* return the port pin data register for a gpio */
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static inline u32 __mcf_gpio_ppdr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADAT;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADAT;
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else if (gpio < 32)
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return MCFSIM_PBDAT;
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else
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return MCFSIM_PCDAT;
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#elif defined(CONFIG_M5249)
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if (gpio < 32)
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return MCFSIM2_GPIOREAD;
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else
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return MCFSIM2_GPIO1READ;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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if (gpio < 8)
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return MCFEPORT_EPPDR;
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#if defined(CONFIG_M528x)
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else if (gpio < 16)
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return MCFGPTA_GPTPORT;
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else if (gpio < 24)
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return MCFGPTB_GPTPORT;
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else if (gpio < 32)
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return MCFQADC_PORTQA;
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else if (gpio < 40)
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return MCFQADC_PORTQB;
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#endif
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else
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return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#endif
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}
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/* return the port output data register for a gpio */
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static inline u32 __mcf_gpio_podr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADAT;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADAT;
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else if (gpio < 32)
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return MCFSIM_PBDAT;
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else
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return MCFSIM_PCDAT;
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#elif defined(CONFIG_M5249)
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if (gpio < 32)
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return MCFSIM2_GPIOWRITE;
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else
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return MCFSIM2_GPIO1WRITE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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if (gpio < 8)
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return MCFEPORT_EPDR;
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#if defined(CONFIG_M528x)
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else if (gpio < 16)
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return MCFGPTA_GPTPORT;
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else if (gpio < 24)
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return MCFGPTB_GPTPORT;
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else if (gpio < 32)
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return MCFQADC_PORTQA;
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else if (gpio < 40)
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return MCFQADC_PORTQB;
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#endif
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else
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return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#endif
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}
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/*
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* The Generic GPIO functions
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*
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* If the gpio is a compile time constant and is one of the Coldfire gpios,
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* use the inline version, otherwise dispatch thru gpiolib.
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*/
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static inline int gpio_get_value(unsigned gpio)
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{
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if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
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return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
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else
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) {
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if (gpio < MCFGPIO_SCR_START) {
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unsigned long flags;
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MCFGPIO_PORTTYPE data;
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local_irq_save(flags);
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data = mcfgpio_read(__mcf_gpio_podr(gpio));
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if (value)
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data |= mcfgpio_bit(gpio);
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else
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data &= ~mcfgpio_bit(gpio);
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mcfgpio_write(data, __mcf_gpio_podr(gpio));
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local_irq_restore(flags);
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} else {
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if (value)
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mcfgpio_write(mcfgpio_bit(gpio),
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MCFGPIO_SETR_PORT(gpio));
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else
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mcfgpio_write(~mcfgpio_bit(gpio),
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MCFGPIO_CLRR_PORT(gpio));
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}
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} else
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__gpio_set_value(gpio, value);
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}
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static inline int gpio_to_irq(unsigned gpio)
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{
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return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE : -EINVAL;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return (irq >= MCFGPIO_IRQ_VECBASE &&
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irq < (MCFGPIO_IRQ_VECBASE + MCFGPIO_IRQ_MAX)) ?
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irq - MCFGPIO_IRQ_VECBASE : -ENXIO;
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}
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static inline int gpio_cansleep(unsigned gpio)
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{
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return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
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}
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#endif
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