77e196752b
The amount of video memory size is decided according to the following order: 1. <xres> x <yres> x <bits_per_pixel> by default, which is the backward compatible way 2. size specified in platform data 3. size specified in module parameter 'options' string or specified in kernel boot command line (see updated Documentation/fb/pxafb.txt) And now since the memory is allocated from system memory, the pxafb_mmap can be removed and the default fb_mmap() should be working all right. Also, since we now have introduced the 'struct pxafb_dma_buff' for DMA descriptors and palettes, the allocation can be separated cleanly. NOTE: the LCD DMA actually supports chained transfer (i.e. page-based transfers), to simplify the logic and keep the performance (with less TLB misses when accessing from memory mapped user space), the memory is allocated by alloc_pages_*() to ensures it's physical contiguous. Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Eric Miao <ycmiao@ycmiao-hp520.(none)>
58 lines
1.4 KiB
Text
58 lines
1.4 KiB
Text
Driver for PXA25x LCD controller
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================================
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The driver supports the following options, either via
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options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in.
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For example:
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modprobe pxafb options=vmem:2M,mode:640x480-8,passive
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or on the kernel command line
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video=pxafb:vmem:2M,mode:640x480-8,passive
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vmem: VIDEO_MEM_SIZE
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Amount of video memory to allocate (can be suffixed with K or M
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for kilobytes or megabytes)
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mode:XRESxYRES[-BPP]
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XRES == LCCR1_PPL + 1
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YRES == LLCR2_LPP + 1
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The resolution of the display in pixels
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BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
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pixclock:PIXCLOCK
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Pixel clock in picoseconds
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left:LEFT == LCCR1_BLW + 1
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right:RIGHT == LCCR1_ELW + 1
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hsynclen:HSYNC == LCCR1_HSW + 1
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upper:UPPER == LCCR2_BFW
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lower:LOWER == LCCR2_EFR
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vsynclen:VSYNC == LCCR2_VSW + 1
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Display margins and sync times
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color | mono => LCCR0_CMS
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umm...
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active | passive => LCCR0_PAS
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Active (TFT) or Passive (STN) display
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single | dual => LCCR0_SDS
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Single or dual panel passive display
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4pix | 8pix => LCCR0_DPD
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4 or 8 pixel monochrome single panel data
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hsync:HSYNC
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vsync:VSYNC
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Horizontal and vertical sync. 0 => active low, 1 => active
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high.
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dpc:DPC
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Double pixel clock. 1=>true, 0=>false
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outputen:POLARITY
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Output Enable Polarity. 0 => active low, 1 => active high
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pixclockpol:POLARITY
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pixel clock polarity
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0 => falling edge, 1 => rising edge
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