74eee2e8d0
The PHY on 82577/82578 parts needs a soft reset when transitioning to Sx state in order for the PHY write which disables gigabit speed to take effect. Gigabit speed must be disabled in order for the PHY writes to registers on page 800 (the wakeup control registers) to work as expected otherwise the system might not wake via WoL. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| 82571.c | ||
| defines.h | ||
| e1000.h | ||
| es2lan.c | ||
| ethtool.c | ||
| hw.h | ||
| ich8lan.c | ||
| lib.c | ||
| Makefile | ||
| netdev.c | ||
| param.c | ||
| phy.c | ||