657ebfadc1
clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
145 lines
3.5 KiB
C
145 lines
3.5 KiB
C
/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock3xxx.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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{
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/*
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* According to the 12-5 CDP code from TI, "Limitation 2.5"
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* on 3430ES1 prevents us from changing DPLL multipliers or dividers
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* on DPLL4.
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*/
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if (omap_rev() == OMAP3430_REV_ES1_0) {
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pr_err("clock: DPLL4 cannot change rate due to "
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"silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate(clk, rate);
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}
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_enable(dpll5_clk);
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/* Enable autoidle to allow it to enter low power bypass */
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omap3_dpll_allow_idle(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable(dpll5_m2_clk);
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clk_disable(dpll5_clk);
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return;
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}
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/* Common clock code */
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/* REVISIT: Move this init stuff out into clock.c */
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap3xxx_clk_arch_init(void)
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{
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struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
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unsigned long osc_sys_rate;
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bool err = 0;
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if (!cpu_is_omap34xx())
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return 0;
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if (!mpurate)
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return -EINVAL;
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/* XXX test these for success */
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dpll1_ck = clk_get(NULL, "dpll1_ck");
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if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))
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err = 1;
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arm_fck = clk_get(NULL, "arm_fck");
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if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
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err = 1;
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core_ck = clk_get(NULL, "core_ck");
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if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))
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err = 1;
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osc_sys_ck = clk_get(NULL, "osc_sys_ck");
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if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))
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err = 1;
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if (err)
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return -ENOENT;
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/* REVISIT: not yet ready for 343x */
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if (clk_set_rate(dpll1_ck, mpurate))
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printk(KERN_ERR "*** Unable to set MPU rate\n");
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recalculate_root_clocks();
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osc_sys_rate = clk_get_rate(osc_sys_ck);
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pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_rate / 1000000),
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((osc_sys_rate / 100000) % 10),
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(clk_get_rate(core_ck) / 1000000),
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(clk_get_rate(arm_fck) / 1000000));
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calibrate_delay();
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return 0;
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}
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arch_initcall(omap3xxx_clk_arch_init);
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