7948758d27
v2. moved nv44 pciegart table back to instmem, where it's not
accessible by userspace clients.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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void
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nv40_fb_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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switch (dev_priv->chipset) {
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case 0x40:
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nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
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break;
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default:
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nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
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break;
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}
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}
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static void
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nv40_fb_init_gart(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
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if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
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nv_wr32(dev, 0x100800, 0x00000001);
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return;
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}
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nv_wr32(dev, 0x100800, gart->pinst | 0x00000002);
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nv_mask(dev, 0x10008c, 0x00000100, 0x00000100);
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nv_wr32(dev, 0x100820, 0x00000000);
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}
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static void
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nv44_fb_init_gart(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
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u32 vinst;
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if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
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nv_wr32(dev, 0x100850, 0x80000000);
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nv_wr32(dev, 0x100800, 0x00000001);
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return;
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}
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/* calculate vram address of this PRAMIN block, object
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* must be allocated on 512KiB alignment, and not exceed
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* a total size of 512KiB for this to work correctly
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*/
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vinst = nv_rd32(dev, 0x10020c);
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vinst -= ((gart->pinst >> 19) + 1) << 19;
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nv_wr32(dev, 0x100850, 0x80000000);
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nv_wr32(dev, 0x100818, dev_priv->gart_info.dummy.addr);
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nv_wr32(dev, 0x100804, dev_priv->gart_info.aper_size);
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nv_wr32(dev, 0x100850, 0x00008000);
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nv_mask(dev, 0x10008c, 0x00000200, 0x00000200);
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nv_wr32(dev, 0x100820, 0x00000000);
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nv_wr32(dev, 0x10082c, 0x00000001);
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nv_wr32(dev, 0x100800, vinst | 0x00000010);
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}
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int
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nv40_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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uint32_t tmp;
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int i;
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if (dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) {
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if (nv44_graph_class(dev))
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nv44_fb_init_gart(dev);
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else
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nv40_fb_init_gart(dev);
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}
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
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nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
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pfb->num_tiles = NV10_PFB_TILE__SIZE;
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break;
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case 0x46: /* G72 */
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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case 0x4c: /* C51 (G7X version) */
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pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
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break;
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default:
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pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
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break;
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}
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->set_tile_region(dev, i);
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return 0;
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}
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void
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nv40_fb_takedown(struct drm_device *dev)
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{
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}
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