aa8f0dc6c3
Jens Axboe pointed out that the iounmap() call in libata was occurring too early, and some drivers (ahci, probably others) were using ioremap'd memory after it had been unmapped. The patch should address that problem by way of improving the libata driver API: * move ->host_stop() call after all ->port_stop() calls have occurred. * create default helper function ata_host_stop(), and move iounmap() call there. * add ->host_stop_prewalk() hook, use it in sata_qstor.c (hi Mark). sata_qstor appears to require the host-stop-before-port-stop ordering that existed prior to applying the attached patch.
685 lines
17 KiB
C
685 lines
17 KiB
C
/*
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* sata_promise.c - Promise SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc.
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*
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* The contents of this file are subject to the Open
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* Software License version 1.1 that can be found at
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* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
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* by reference.
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the GNU General Public License version 2 (the "GPL") as distributed
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* in the kernel source COPYING file, in which case the provisions of
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* the GPL are applicable instead of the above. If you wish to allow
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* the use of your version of this file only under the terms of the
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* GPL and not to allow others to use your version of this file under
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* the OSL, indicate your decision by deleting the provisions above and
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* replace them with the notice and other provisions required by the GPL.
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* If you do not delete the provisions above, a recipient may use your
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* version of this file under either the OSL or the GPL.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <asm/io.h>
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#include "sata_promise.h"
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#define DRV_NAME "sata_promise"
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#define DRV_VERSION "1.01"
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enum {
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PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_TBG_MODE = 0x41, /* TBG mode */
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PDC_FLASH_CTL = 0x44, /* Flash control register */
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PDC_PCI_CTL = 0x48, /* PCI control and status register */
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PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
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PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
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PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
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PDC_SLEW_CTL = 0x470, /* slew rate control reg */
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PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
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(1<<8) | (1<<9) | (1<<10),
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board_2037x = 0, /* FastTrak S150 TX2plus */
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board_20319 = 1, /* FastTrak S150 TX4 */
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PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
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PDC_RESET = (1 << 11), /* HDMA reset */
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};
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struct pdc_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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};
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
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static void pdc_eng_timeout(struct ata_port *ap);
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static int pdc_port_start(struct ata_port *ap);
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static void pdc_port_stop(struct ata_port *ap);
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static void pdc_phy_reset(struct ata_port *ap);
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static void pdc_qc_prep(struct ata_queued_cmd *qc);
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static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
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static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
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static void pdc_irq_clear(struct ata_port *ap);
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static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
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static Scsi_Host_Template pdc_ata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.ordered_flush = 1,
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};
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static struct ata_port_operations pdc_ata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.phy_reset = pdc_phy_reset,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.eng_timeout = pdc_eng_timeout,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.scr_read = pdc_sata_scr_read,
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.scr_write = pdc_sata_scr_write,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_info pdc_port_info[] = {
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/* board_2037x */
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{
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.sht = &pdc_ata_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SRST | ATA_FLAG_MMIO,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_ata_ops,
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},
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/* board_20319 */
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{
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.sht = &pdc_ata_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SRST | ATA_FLAG_MMIO,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_ata_ops,
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},
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};
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static struct pci_device_id pdc_ata_pci_tbl[] = {
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{ PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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{ PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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{ PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20319 },
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{ } /* terminate list */
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};
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static struct pci_driver pdc_ata_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc_ata_pci_tbl,
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.probe = pdc_ata_init_one,
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.remove = ata_pci_remove_one,
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};
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static int pdc_port_start(struct ata_port *ap)
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{
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struct device *dev = ap->host_set->dev;
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struct pdc_port_priv *pp;
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int rc;
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rc = ata_port_start(ap);
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if (rc)
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return rc;
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pp = kmalloc(sizeof(*pp), GFP_KERNEL);
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if (!pp) {
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rc = -ENOMEM;
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goto err_out;
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}
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memset(pp, 0, sizeof(*pp));
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pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
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if (!pp->pkt) {
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rc = -ENOMEM;
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goto err_out_kfree;
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}
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ap->private_data = pp;
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return 0;
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err_out_kfree:
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kfree(pp);
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err_out:
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ata_port_stop(ap);
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return rc;
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}
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static void pdc_port_stop(struct ata_port *ap)
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{
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struct device *dev = ap->host_set->dev;
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struct pdc_port_priv *pp = ap->private_data;
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ap->private_data = NULL;
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dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
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kfree(pp);
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ata_port_stop(ap);
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}
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static void pdc_reset_port(struct ata_port *ap)
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{
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void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
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unsigned int i;
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u32 tmp;
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for (i = 11; i > 0; i--) {
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tmp = readl(mmio);
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if (tmp & PDC_RESET)
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break;
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udelay(100);
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tmp |= PDC_RESET;
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writel(tmp, mmio);
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}
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tmp &= ~PDC_RESET;
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writel(tmp, mmio);
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readl(mmio); /* flush */
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}
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static void pdc_phy_reset(struct ata_port *ap)
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{
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pdc_reset_port(ap);
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sata_phy_reset(ap);
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}
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
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u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void pdc_qc_prep(struct ata_queued_cmd *qc)
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{
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struct pdc_port_priv *pp = qc->ap->private_data;
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unsigned int i;
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VPRINTK("ENTER\n");
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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ata_qc_prep(qc);
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/* fall through */
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case ATA_PROT_NODATA:
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i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
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qc->dev->devno, pp->pkt);
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if (qc->tf.flags & ATA_TFLAG_LBA48)
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i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
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else
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i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
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pdc_pkt_footer(&qc->tf, pp->pkt, i);
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break;
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default:
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break;
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}
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}
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static void pdc_eng_timeout(struct ata_port *ap)
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{
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u8 drv_stat;
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struct ata_queued_cmd *qc;
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DPRINTK("ENTER\n");
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (!qc) {
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printk(KERN_ERR "ata%u: BUG: timeout without command\n",
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ap->id);
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goto out;
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}
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/* hack alert! We cannot use the supplied completion
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* function from inside the ->eh_strategy_handler() thread.
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* libata is the only user of ->eh_strategy_handler() in
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* any kernel, so the default scsi_done() assumes it is
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* not being called from the SCSI EH.
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*/
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qc->scsidone = scsi_finish_command;
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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case ATA_PROT_NODATA:
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printk(KERN_ERR "ata%u: command timeout\n", ap->id);
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ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
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break;
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default:
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drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
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printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
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ap->id, qc->tf.command, drv_stat);
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ata_qc_complete(qc, drv_stat);
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break;
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}
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out:
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DPRINTK("EXIT\n");
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}
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static inline unsigned int pdc_host_intr( struct ata_port *ap,
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struct ata_queued_cmd *qc)
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{
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u8 status;
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unsigned int handled = 0, have_err = 0;
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u32 tmp;
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void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
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tmp = readl(mmio);
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if (tmp & PDC_ERR_MASK) {
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have_err = 1;
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pdc_reset_port(ap);
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}
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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case ATA_PROT_NODATA:
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status = ata_wait_idle(ap);
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if (have_err)
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status |= ATA_ERR;
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ata_qc_complete(qc, status);
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handled = 1;
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break;
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default:
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ap->stats.idle_irq++;
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break;
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}
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return handled;
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}
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static void pdc_irq_clear(struct ata_port *ap)
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{
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struct ata_host_set *host_set = ap->host_set;
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void *mmio = host_set->mmio_base;
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readl(mmio + PDC_INT_SEQMASK);
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}
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static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ata_host_set *host_set = dev_instance;
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struct ata_port *ap;
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u32 mask = 0;
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unsigned int i, tmp;
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unsigned int handled = 0;
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void *mmio_base;
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VPRINTK("ENTER\n");
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if (!host_set || !host_set->mmio_base) {
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VPRINTK("QUICK EXIT\n");
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return IRQ_NONE;
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}
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mmio_base = host_set->mmio_base;
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/* reading should also clear interrupts */
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mask = readl(mmio_base + PDC_INT_SEQMASK);
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if (mask == 0xffffffff) {
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VPRINTK("QUICK EXIT 2\n");
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return IRQ_NONE;
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}
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mask &= 0xffff; /* only 16 tags possible */
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if (!mask) {
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VPRINTK("QUICK EXIT 3\n");
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return IRQ_NONE;
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}
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spin_lock(&host_set->lock);
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writel(mask, mmio_base + PDC_INT_SEQMASK);
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for (i = 0; i < host_set->n_ports; i++) {
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VPRINTK("port %u\n", i);
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ap = host_set->ports[i];
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tmp = mask & (1 << (i + 1));
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if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc && (!(qc->tf.ctl & ATA_NIEN)))
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handled += pdc_host_intr(ap, qc);
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}
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}
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spin_unlock(&host_set->lock);
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VPRINTK("EXIT\n");
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return IRQ_RETVAL(handled);
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}
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static inline void pdc_packet_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct pdc_port_priv *pp = ap->private_data;
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unsigned int port_no = ap->port_no;
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u8 seq = (u8) (port_no + 1);
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VPRINTK("ENTER, ap %p\n", ap);
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writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
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readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
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pp->pkt[2] = seq;
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wmb(); /* flush PRD, pkt writes */
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writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
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readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
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}
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static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
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{
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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case ATA_PROT_NODATA:
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pdc_packet_start(qc);
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return 0;
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|
|
|
case ATA_PROT_ATAPI_DMA:
|
|
BUG();
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ata_qc_issue_prot(qc);
|
|
}
|
|
|
|
static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
|
|
{
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
ata_tf_load(ap, tf);
|
|
}
|
|
|
|
|
|
static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
|
|
{
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
ata_exec_command(ap, tf);
|
|
}
|
|
|
|
|
|
static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
|
|
{
|
|
port->cmd_addr = base;
|
|
port->data_addr = base;
|
|
port->feature_addr =
|
|
port->error_addr = base + 0x4;
|
|
port->nsect_addr = base + 0x8;
|
|
port->lbal_addr = base + 0xc;
|
|
port->lbam_addr = base + 0x10;
|
|
port->lbah_addr = base + 0x14;
|
|
port->device_addr = base + 0x18;
|
|
port->command_addr =
|
|
port->status_addr = base + 0x1c;
|
|
port->altstatus_addr =
|
|
port->ctl_addr = base + 0x38;
|
|
}
|
|
|
|
|
|
static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
|
|
{
|
|
void *mmio = pe->mmio_base;
|
|
u32 tmp;
|
|
|
|
/*
|
|
* Except for the hotplug stuff, this is voodoo from the
|
|
* Promise driver. Label this entire section
|
|
* "TODO: figure out why we do this"
|
|
*/
|
|
|
|
/* change FIFO_SHD to 8 dwords, enable BMR_BURST */
|
|
tmp = readl(mmio + PDC_FLASH_CTL);
|
|
tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
|
|
writel(tmp, mmio + PDC_FLASH_CTL);
|
|
|
|
/* clear plug/unplug flags for all ports */
|
|
tmp = readl(mmio + PDC_SATA_PLUG_CSR);
|
|
writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
|
|
|
|
/* mask plug/unplug ints */
|
|
tmp = readl(mmio + PDC_SATA_PLUG_CSR);
|
|
writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
|
|
|
|
/* reduce TBG clock to 133 Mhz. */
|
|
tmp = readl(mmio + PDC_TBG_MODE);
|
|
tmp &= ~0x30000; /* clear bit 17, 16*/
|
|
tmp |= 0x10000; /* set bit 17:16 = 0:1 */
|
|
writel(tmp, mmio + PDC_TBG_MODE);
|
|
|
|
readl(mmio + PDC_TBG_MODE); /* flush */
|
|
msleep(10);
|
|
|
|
/* adjust slew rate control register. */
|
|
tmp = readl(mmio + PDC_SLEW_CTL);
|
|
tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
|
|
tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
|
|
writel(tmp, mmio + PDC_SLEW_CTL);
|
|
}
|
|
|
|
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
static int printed_version;
|
|
struct ata_probe_ent *probe_ent = NULL;
|
|
unsigned long base;
|
|
void *mmio_base;
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
int pci_dev_busy = 0;
|
|
int rc;
|
|
|
|
if (!printed_version++)
|
|
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
|
|
|
|
/*
|
|
* If this driver happens to only be useful on Apple's K2, then
|
|
* we should check that here as it has a normal Serverworks ID
|
|
*/
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
if (rc) {
|
|
pci_dev_busy = 1;
|
|
goto err_out;
|
|
}
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
|
|
probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
|
|
if (probe_ent == NULL) {
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
memset(probe_ent, 0, sizeof(*probe_ent));
|
|
probe_ent->dev = pci_dev_to_dev(pdev);
|
|
INIT_LIST_HEAD(&probe_ent->node);
|
|
|
|
mmio_base = ioremap(pci_resource_start(pdev, 3),
|
|
pci_resource_len(pdev, 3));
|
|
if (mmio_base == NULL) {
|
|
rc = -ENOMEM;
|
|
goto err_out_free_ent;
|
|
}
|
|
base = (unsigned long) mmio_base;
|
|
|
|
probe_ent->sht = pdc_port_info[board_idx].sht;
|
|
probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
|
|
probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
|
|
probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
|
|
probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
|
|
probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
|
|
|
|
probe_ent->irq = pdev->irq;
|
|
probe_ent->irq_flags = SA_SHIRQ;
|
|
probe_ent->mmio_base = mmio_base;
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
|
|
pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
|
|
|
|
probe_ent->port[0].scr_addr = base + 0x400;
|
|
probe_ent->port[1].scr_addr = base + 0x500;
|
|
|
|
/* notice 4-port boards */
|
|
switch (board_idx) {
|
|
case board_20319:
|
|
probe_ent->n_ports = 4;
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
probe_ent->port[2].scr_addr = base + 0x600;
|
|
probe_ent->port[3].scr_addr = base + 0x700;
|
|
break;
|
|
case board_2037x:
|
|
probe_ent->n_ports = 2;
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* initialize adapter */
|
|
pdc_host_init(board_idx, probe_ent);
|
|
|
|
/* FIXME: check ata_device_add return value */
|
|
ata_device_add(probe_ent);
|
|
kfree(probe_ent);
|
|
|
|
return 0;
|
|
|
|
err_out_free_ent:
|
|
kfree(probe_ent);
|
|
err_out_regions:
|
|
pci_release_regions(pdev);
|
|
err_out:
|
|
if (!pci_dev_busy)
|
|
pci_disable_device(pdev);
|
|
return rc;
|
|
}
|
|
|
|
|
|
static int __init pdc_ata_init(void)
|
|
{
|
|
return pci_module_init(&pdc_ata_pci_driver);
|
|
}
|
|
|
|
|
|
static void __exit pdc_ata_exit(void)
|
|
{
|
|
pci_unregister_driver(&pdc_ata_pci_driver);
|
|
}
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
|
MODULE_DESCRIPTION("Promise SATA TX2/TX4 low-level driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(pdc_ata_init);
|
|
module_exit(pdc_ata_exit);
|