230f984662
Now that most platforms don't need disable_fiq and arch_ret_to_user macros, we can remove the empty macros or empty entry-macro.S files. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ryan Mallon <rmallon@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
76 lines
2.4 KiB
ArmAsm
76 lines
2.4 KiB
ArmAsm
/*****************************************************************************
|
|
* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
|
|
*
|
|
* Unless you and Broadcom execute a separate written software license
|
|
* agreement governing use of this software, this software is licensed to you
|
|
* under the terms of the GNU General Public License version 2, available at
|
|
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
|
*
|
|
* Notwithstanding the above, under no circumstances may you combine this
|
|
* software in any way with any other Broadcom software provided under a
|
|
* license other than the GPL, without Broadcom's express prior written
|
|
* consent.
|
|
*****************************************************************************/
|
|
|
|
/*
|
|
*
|
|
* Low-level IRQ helper macros for BCMRing-based platforms
|
|
*
|
|
*/
|
|
#include <mach/irqs.h>
|
|
#include <mach/hardware.h>
|
|
#include <mach/csp/mm_io.h>
|
|
|
|
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
|
ldr \base, =(MM_IO_BASE_INTC0)
|
|
ldr \irqstat, [\base, #0] @ get status
|
|
ldr \irqnr, [\base, #0x10] @ mask with enable register
|
|
ands \irqstat, \irqstat, \irqnr
|
|
mov \irqnr, #IRQ_INTC0_START
|
|
cmp \irqstat, #0
|
|
bne 1001f
|
|
|
|
ldr \base, =(MM_IO_BASE_INTC1)
|
|
ldr \irqstat, [\base, #0] @ get status
|
|
ldr \irqnr, [\base, #0x10] @ mask with enable register
|
|
ands \irqstat, \irqstat, \irqnr
|
|
mov \irqnr, #IRQ_INTC1_START
|
|
cmp \irqstat, #0
|
|
bne 1001f
|
|
|
|
ldr \base, =(MM_IO_BASE_SINTC)
|
|
ldr \irqstat, [\base, #0] @ get status
|
|
ldr \irqnr, [\base, #0x10] @ mask with enable register
|
|
ands \irqstat, \irqstat, \irqnr
|
|
mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
|
|
cmp \irqstat, #0
|
|
beq 1002f
|
|
|
|
mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
|
|
|
|
1001:
|
|
movs \tmp, \irqstat, lsl #16
|
|
movne \irqstat, \tmp
|
|
addeq \irqnr, \irqnr, #16
|
|
|
|
movs \tmp, \irqstat, lsl #8
|
|
movne \irqstat, \tmp
|
|
addeq \irqnr, \irqnr, #8
|
|
|
|
movs \tmp, \irqstat, lsl #4
|
|
movne \irqstat, \tmp
|
|
addeq \irqnr, \irqnr, #4
|
|
|
|
movs \tmp, \irqstat, lsl #2
|
|
movne \irqstat, \tmp
|
|
addeq \irqnr, \irqnr, #2
|
|
|
|
movs \tmp, \irqstat, lsl #1
|
|
addeq \irqnr, \irqnr, #1
|
|
orrs \base, \base, #1
|
|
|
|
1002: @ irqnr will be set to 0xffffffff if no irq bits are set
|
|
.endm
|
|
|
|
.macro get_irqnr_preamble, base, tmp
|
|
.endm
|