linux/arch/mips/math-emu
Shane McDonald 95e8f634d7 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
    are not currently writeable by the ctc1 instruction.  In odd corner cases,
    this can cause problems.  For example, a case existed where a divide-by-zero
    exception was generated by the FPU, and the signal handler attempted to
    restore the FPU registers to their state before the exception occurred.  In
    this particular setup, writing the old value to the FCSR register would
    cause another divide-by-zero exception to occur immediately.  The solution
    is to change the ctc1 instruction emulator code to allow the Cause bits of
    the FCSR register to be writeable.  This is the behaviour of the hardware
    that the code is emulating.
    
    This problem was found by Shane McDonald, but the credit for the fix goes
    to Kevin Kissell.  In Kevin's words:
    
    I submit that the bug is indeed in that ctc_op:  case of the emulator.  The
    Cause bits (17:12) are supposed to be writable by that instruction, but the
    CTC1 emulation won't let them be updated by the instruction.  I think that
    actually if you just completely removed lines 387-388 [...] things would
    work a good deal better.  At least, it would be a more accurate emulation of
    the architecturally defined FPU.  If I wanted to be really, really pedantic
    (which I sometimes do), I'd also protect the reserved bits that aren't
    necessarily writable.
    
    Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
    To: anemo@mba.ocn.ne.jp
    To: kevink@paralogos.com
    To: sshtylyov@mvista.com
    Patchwork: http://patchwork.linux-mips.org/patch/1205/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2010-05-15 21:59:53 +01:00
..
cp1emu.c MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 2010-05-15 21:59:53 +01:00
dp_add.c
dp_cmp.c
dp_div.c
dp_fint.c
dp_flong.c
dp_frexp.c
dp_fsp.c
dp_logb.c
dp_modf.c
dp_mul.c [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
dp_scalb.c
dp_simple.c MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands 2009-11-02 12:00:05 +01:00
dp_sqrt.c
dp_sub.c tree-wide: fix assorted typos all over the place 2009-12-04 15:39:55 +01:00
dp_tint.c
dp_tlong.c
dsemul.c MIPS: Collect FPU emulator statistics per-CPU. 2009-12-17 01:57:08 +00:00
ieee754.c [MIPS] Compliment va_start() with va_end(). 2007-11-26 17:26:15 +00:00
ieee754.h
ieee754d.c MIPS: Nuke trailing blank lines 2010-02-27 12:53:14 +01:00
ieee754dp.c MIPS: Cleanup switches with cases that can be merged 2010-02-27 12:53:14 +01:00
ieee754dp.h [MIPS] replace __inline with inline 2008-04-28 17:14:26 +01:00
ieee754int.h [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
ieee754m.c
ieee754sp.c MIPS: Cleanup switches with cases that can be merged 2010-02-27 12:53:14 +01:00
ieee754sp.h [MIPS] replace __inline with inline 2008-04-28 17:14:26 +01:00
ieee754xcpt.c MIPS: Nuke trailing blank lines 2010-02-27 12:53:14 +01:00
kernel_linkage.c [MIPS] Fix missing prototypes in asm/fpu.h 2008-07-20 14:38:17 +01:00
Makefile [MIPS] Use -Werror on subdirectories which build cleanly. 2007-07-31 21:35:33 +01:00
sp_add.c
sp_cmp.c
sp_div.c
sp_fdp.c
sp_fint.c
sp_flong.c
sp_frexp.c
sp_logb.c
sp_modf.c
sp_mul.c
sp_scalb.c
sp_simple.c MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands 2009-11-02 12:00:05 +01:00
sp_sqrt.c
sp_sub.c
sp_tint.c
sp_tlong.c