b285192a43
Rename all PCI drivers with their own directory under drivers/media/video into drivers/media/pci and update the building system. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
184 lines
5.8 KiB
C
184 lines
5.8 KiB
C
/*
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* Zoran ZR36050 basic configuration functions - header file
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*
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* Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at>
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*
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* $Id: zr36050.h,v 1.1.2.2 2003/01/14 21:18:22 rbultje Exp $
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*
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* ------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* ------------------------------------------------------------------------
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*/
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#ifndef ZR36050_H
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#define ZR36050_H
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#include "videocodec.h"
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/* data stored for each zoran jpeg codec chip */
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struct zr36050 {
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char name[32];
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int num;
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/* io datastructure */
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struct videocodec *codec;
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// last coder status
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__u8 status1;
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// actual coder setup
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int mode;
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__u16 width;
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__u16 height;
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__u16 bitrate_ctrl;
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__u32 total_code_vol;
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__u32 real_code_vol;
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__u16 max_block_vol;
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__u8 h_samp_ratio[8];
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__u8 v_samp_ratio[8];
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__u16 scalefact;
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__u16 dri;
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/* com/app marker */
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struct jpeg_com_marker com;
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struct jpeg_app_marker app;
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};
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/* zr36050 register addresses */
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#define ZR050_GO 0x000
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#define ZR050_HARDWARE 0x002
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#define ZR050_MODE 0x003
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#define ZR050_OPTIONS 0x004
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#define ZR050_MBCV 0x005
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#define ZR050_MARKERS_EN 0x006
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#define ZR050_INT_REQ_0 0x007
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#define ZR050_INT_REQ_1 0x008
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#define ZR050_TCV_NET_HI 0x009
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#define ZR050_TCV_NET_MH 0x00a
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#define ZR050_TCV_NET_ML 0x00b
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#define ZR050_TCV_NET_LO 0x00c
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#define ZR050_TCV_DATA_HI 0x00d
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#define ZR050_TCV_DATA_MH 0x00e
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#define ZR050_TCV_DATA_ML 0x00f
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#define ZR050_TCV_DATA_LO 0x010
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#define ZR050_SF_HI 0x011
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#define ZR050_SF_LO 0x012
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#define ZR050_AF_HI 0x013
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#define ZR050_AF_M 0x014
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#define ZR050_AF_LO 0x015
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#define ZR050_ACV_HI 0x016
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#define ZR050_ACV_MH 0x017
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#define ZR050_ACV_ML 0x018
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#define ZR050_ACV_LO 0x019
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#define ZR050_ACT_HI 0x01a
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#define ZR050_ACT_MH 0x01b
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#define ZR050_ACT_ML 0x01c
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#define ZR050_ACT_LO 0x01d
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#define ZR050_ACV_TRUN_HI 0x01e
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#define ZR050_ACV_TRUN_MH 0x01f
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#define ZR050_ACV_TRUN_ML 0x020
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#define ZR050_ACV_TRUN_LO 0x021
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#define ZR050_STATUS_0 0x02e
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#define ZR050_STATUS_1 0x02f
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#define ZR050_SOF_IDX 0x040
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#define ZR050_SOS1_IDX 0x07a
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#define ZR050_SOS2_IDX 0x08a
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#define ZR050_SOS3_IDX 0x09a
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#define ZR050_SOS4_IDX 0x0aa
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#define ZR050_DRI_IDX 0x0c0
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#define ZR050_DNL_IDX 0x0c6
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#define ZR050_DQT_IDX 0x0cc
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#define ZR050_DHT_IDX 0x1d4
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#define ZR050_APP_IDX 0x380
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#define ZR050_COM_IDX 0x3c0
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/* zr36050 hardware register bits */
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#define ZR050_HW_BSWD 0x80
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#define ZR050_HW_MSTR 0x40
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#define ZR050_HW_DMA 0x20
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#define ZR050_HW_CFIS_1_CLK 0x00
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#define ZR050_HW_CFIS_2_CLK 0x04
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#define ZR050_HW_CFIS_3_CLK 0x08
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#define ZR050_HW_CFIS_4_CLK 0x0C
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#define ZR050_HW_CFIS_5_CLK 0x10
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#define ZR050_HW_CFIS_6_CLK 0x14
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#define ZR050_HW_CFIS_7_CLK 0x18
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#define ZR050_HW_CFIS_8_CLK 0x1C
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#define ZR050_HW_BELE 0x01
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/* zr36050 mode register bits */
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#define ZR050_MO_COMP 0x80
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#define ZR050_MO_COMP 0x80
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#define ZR050_MO_ATP 0x40
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#define ZR050_MO_PASS2 0x20
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#define ZR050_MO_TLM 0x10
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#define ZR050_MO_DCONLY 0x08
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#define ZR050_MO_BRC 0x04
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#define ZR050_MO_ATP 0x40
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#define ZR050_MO_PASS2 0x20
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#define ZR050_MO_TLM 0x10
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#define ZR050_MO_DCONLY 0x08
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/* zr36050 option register bits */
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#define ZR050_OP_NSCN_1 0x00
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#define ZR050_OP_NSCN_2 0x20
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#define ZR050_OP_NSCN_3 0x40
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#define ZR050_OP_NSCN_4 0x60
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#define ZR050_OP_NSCN_5 0x80
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#define ZR050_OP_NSCN_6 0xA0
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#define ZR050_OP_NSCN_7 0xC0
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#define ZR050_OP_NSCN_8 0xE0
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#define ZR050_OP_OVF 0x10
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/* zr36050 markers-enable register bits */
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#define ZR050_ME_APP 0x80
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#define ZR050_ME_COM 0x40
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#define ZR050_ME_DRI 0x20
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#define ZR050_ME_DQT 0x10
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#define ZR050_ME_DHT 0x08
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#define ZR050_ME_DNL 0x04
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#define ZR050_ME_DQTI 0x02
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#define ZR050_ME_DHTI 0x01
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/* zr36050 status0/1 register bit masks */
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#define ZR050_ST_RST_MASK 0x20
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#define ZR050_ST_SOF_MASK 0x02
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#define ZR050_ST_SOS_MASK 0x02
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#define ZR050_ST_DATRDY_MASK 0x80
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#define ZR050_ST_MRKDET_MASK 0x40
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#define ZR050_ST_RFM_MASK 0x10
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#define ZR050_ST_RFD_MASK 0x08
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#define ZR050_ST_END_MASK 0x04
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#define ZR050_ST_TCVOVF_MASK 0x02
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#define ZR050_ST_DATOVF_MASK 0x01
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/* pixel component idx */
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#define ZR050_Y_COMPONENT 0
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#define ZR050_U_COMPONENT 1
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#define ZR050_V_COMPONENT 2
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#endif /*fndef ZR36050_H */
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