Vishwanath BS 678bc9a2ea OMAP3 clock: Introduce 3630 DPLL4 HSDivider changes ... Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>		2010-02-24 12:15:03 -07:00
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plat	OMAP3 clock: Introduce 3630 DPLL4 HSDivider changes	2010-02-24 12:15:03 -07:00