970a61363b
As we don't support hotplug we end up leaking an isa_dev reference which if unload was ever added we would drop at the end of unloading. This is fine because we do genuinely need the isa_dev pointer until unload. Signed-off-by: Alan Cox <alan@redhat.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
678 lines
19 KiB
C
678 lines
19 KiB
C
/*
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* linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
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*
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* Copyright (C) 1998-2000 Michel Aubry
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* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Portions copyright (c) 2001 Sun Microsystems
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*
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*
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* RCC/ServerWorks IDE driver for Linux
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*
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* OSB4: `Open South Bridge' IDE Interface (fn 1)
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* supports UDMA mode 2 (33 MB/s)
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*
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* CSB5: `Champion South Bridge' IDE Interface (fn 1)
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* all revisions support UDMA mode 4 (66 MB/s)
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* revision A2.0 and up support UDMA mode 5 (100 MB/s)
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*
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* *** The CSB5 does not provide ANY register ***
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* *** to detect 80-conductor cable presence. ***
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*
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* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
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*
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* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
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* controller same as the CSB6. Single channel ATA100 only.
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*
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* Documentation:
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* Available under NDA only. Errata info very hard to get.
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
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#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
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/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
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* can overrun their FIFOs when used with the CSB5 */
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static const char *svwks_bad_ata100[] = {
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"ST320011A",
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"ST340016A",
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"ST360021A",
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"ST380021A",
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NULL
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};
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static u8 svwks_revision = 0;
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static struct pci_dev *isa_dev;
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static int check_in_drive_lists (ide_drive_t *drive, const char **list)
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{
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while (*list)
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if (!strcmp(*list++, drive->id->model))
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return 1;
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return 0;
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}
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static u8 svwks_ratemask (ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u8 mode = 0;
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if (!svwks_revision)
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pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
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return 2;
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
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u32 reg = 0;
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if (isa_dev)
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pci_read_config_dword(isa_dev, 0x64, ®);
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/*
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* Don't enable UDMA on disk devices for the moment
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*/
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if(drive->media == ide_disk)
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return 0;
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/* Check the OSB4 DMA33 enable bit */
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return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
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} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
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return 1;
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} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
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u8 btr = 0;
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pci_read_config_byte(dev, 0x5A, &btr);
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mode = btr & 0x3;
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if (!eighty_ninty_three(drive))
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mode = min(mode, (u8)1);
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/* If someone decides to do UDMA133 on CSB5 the same
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issue will bite so be inclusive */
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if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
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mode = 2;
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}
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if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
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(!(PCI_FUNC(dev->devfn) & 1)))
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mode = 2;
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return mode;
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}
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static u8 svwks_csb_check (struct pci_dev *dev)
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{
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switch (dev->device) {
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case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
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case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
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return 1;
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default:
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break;
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}
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return 0;
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}
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static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
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static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
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static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
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static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
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static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 speed;
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u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 csb5 = svwks_csb_check(dev);
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u8 ultra_enable = 0, ultra_timing = 0;
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u8 dma_timing = 0, pio_timing = 0;
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u16 csb5_pio = 0;
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if (xferspeed == 255) /* PIO auto-tuning */
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speed = XFER_PIO_0 + pio;
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else
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speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
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/* If we are about to put a disk into UDMA mode we screwed up.
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Our code assumes we never _ever_ do this on an OSB4 */
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if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
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drive->media == ide_disk && speed >= XFER_UDMA_0)
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BUG();
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pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
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pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
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pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
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pci_read_config_word(dev, 0x4A, &csb5_pio);
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pci_read_config_byte(dev, 0x54, &ultra_enable);
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/* Per Specified Design by OEM, and ASIC Architect */
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if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
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if (!drive->init_speed) {
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u8 dma_stat = hwif->INB(hwif->dma_status);
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dma_pio:
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if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
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((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
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drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
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return 0;
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} else if ((dma_timing) &&
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((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
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u8 dmaspeed = dma_timing;
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dma_timing &= ~0xFF;
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if ((dmaspeed & 0x20) == 0x20)
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dmaspeed = XFER_MW_DMA_2;
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else if ((dmaspeed & 0x21) == 0x21)
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dmaspeed = XFER_MW_DMA_1;
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else if ((dmaspeed & 0x77) == 0x77)
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dmaspeed = XFER_MW_DMA_0;
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else
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goto dma_pio;
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drive->current_speed = drive->init_speed = dmaspeed;
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return 0;
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} else if (pio_timing) {
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u8 piospeed = pio_timing;
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pio_timing &= ~0xFF;
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if ((piospeed & 0x20) == 0x20)
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piospeed = XFER_PIO_4;
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else if ((piospeed & 0x22) == 0x22)
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piospeed = XFER_PIO_3;
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else if ((piospeed & 0x34) == 0x34)
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piospeed = XFER_PIO_2;
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else if ((piospeed & 0x47) == 0x47)
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piospeed = XFER_PIO_1;
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else if ((piospeed & 0x5d) == 0x5d)
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piospeed = XFER_PIO_0;
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else
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goto oem_setup_failed;
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drive->current_speed = drive->init_speed = piospeed;
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return 0;
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}
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}
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}
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oem_setup_failed:
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pio_timing &= ~0xFF;
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dma_timing &= ~0xFF;
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ultra_timing &= ~(0x0F << (4*unit));
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ultra_enable &= ~(0x01 << drive->dn);
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csb5_pio &= ~(0x0F << (4*drive->dn));
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switch(speed) {
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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pio_timing |= pio_modes[speed - XFER_PIO_0];
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csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
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break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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pio_timing |= pio_modes[pio];
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csb5_pio |= (pio << (4*drive->dn));
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dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
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break;
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case XFER_UDMA_5:
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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pio_timing |= pio_modes[pio];
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csb5_pio |= (pio << (4*drive->dn));
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dma_timing |= dma_modes[2];
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ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
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ultra_enable |= (0x01 << drive->dn);
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default:
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break;
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}
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pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
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if (csb5)
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pci_write_config_word(dev, 0x4A, csb5_pio);
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pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
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pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
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pci_write_config_byte(dev, 0x54, ultra_enable);
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return (ide_config_drive_speed(drive, speed));
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}
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static void config_chipset_for_pio (ide_drive_t *drive)
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{
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u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
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u16 xfer_pio = drive->id->eide_pio_modes;
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u8 timing, speed, pio;
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pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
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if (xfer_pio > 4)
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xfer_pio = 0;
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if (drive->id->eide_pio_iordy > 0)
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for (xfer_pio = 5;
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xfer_pio>0 &&
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drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
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xfer_pio--);
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else
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xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
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(drive->id->eide_pio_modes & 2) ? 0x04 :
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(drive->id->eide_pio_modes & 1) ? 0x03 :
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(drive->id->tPIO & 2) ? 0x02 :
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(drive->id->tPIO & 1) ? 0x01 : xfer_pio;
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timing = (xfer_pio >= pio) ? xfer_pio : pio;
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switch(timing) {
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case 4: speed = XFER_PIO_4;break;
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case 3: speed = XFER_PIO_3;break;
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case 2: speed = XFER_PIO_2;break;
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case 1: speed = XFER_PIO_1;break;
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default:
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speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
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break;
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}
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(void) svwks_tune_chipset(drive, speed);
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drive->current_speed = speed;
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}
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static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
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{
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if(pio == 255)
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(void) svwks_tune_chipset(drive, 255);
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else
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(void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
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}
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static int config_chipset_for_dma (ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
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if (!(speed))
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speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
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(void) svwks_tune_chipset(drive, speed);
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return ide_dma_enable(drive);
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}
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static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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drive->init_speed = 0;
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (config_chipset_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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config_chipset_for_pio(drive);
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// hwif->tuneproc(drive, 5);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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/* This can go soon */
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static int svwks_ide_dma_end (ide_drive_t *drive)
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{
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return __ide_dma_end(drive);
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}
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static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
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{
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unsigned int reg;
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u8 btr;
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/* save revision id to determine DMA capability */
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pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
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/* force Master Latency Timer value to 64 PCICLKs */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
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/* OSB4 : South Bridge and IDE */
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if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
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isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
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if (isa_dev) {
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pci_read_config_dword(isa_dev, 0x64, ®);
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reg &= ~0x00002000; /* disable 600ns interrupt mask */
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if(!(reg & 0x00004000))
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printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
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reg |= 0x00004000; /* enable UDMA/33 support */
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pci_write_config_dword(isa_dev, 0x64, reg);
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}
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}
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/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
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else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
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(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
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/* Third Channel Test */
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if (!(PCI_FUNC(dev->devfn) & 1)) {
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struct pci_dev * findev = NULL;
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u32 reg4c = 0;
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
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if (findev) {
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pci_read_config_dword(findev, 0x4C, ®4c);
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reg4c &= ~0x000007FF;
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reg4c |= 0x00000040;
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reg4c |= 0x00000020;
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pci_write_config_dword(findev, 0x4C, reg4c);
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pci_dev_put(findev);
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}
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outb_p(0x06, 0x0c00);
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dev->irq = inb_p(0x0c01);
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} else {
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struct pci_dev * findev = NULL;
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u8 reg41 = 0;
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
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PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
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if (findev) {
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pci_read_config_byte(findev, 0x41, ®41);
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reg41 &= ~0x40;
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pci_write_config_byte(findev, 0x41, reg41);
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pci_dev_put(findev);
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}
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/*
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* This is a device pin issue on CSB6.
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* Since there will be a future raid mode,
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* early versions of the chipset require the
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* interrupt pin to be set, and it is a compatibility
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* mode issue.
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*/
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
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dev->irq = 0;
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}
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// pci_read_config_dword(dev, 0x40, &pioreg)
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// pci_write_config_dword(dev, 0x40, 0x99999999);
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// pci_read_config_dword(dev, 0x44, &dmareg);
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// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
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/* setup the UDMA Control register
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*
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* 1. clear bit 6 to enable DMA
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* 2. enable DMA modes with bits 0-1
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* 00 : legacy
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* 01 : udma2
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* 10 : udma2/udma4
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* 11 : udma2/udma4/udma5
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*/
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pci_read_config_byte(dev, 0x5A, &btr);
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btr &= ~0x40;
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if (!(PCI_FUNC(dev->devfn) & 1))
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btr |= 0x2;
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else
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btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
|
|
pci_write_config_byte(dev, 0x5A, btr);
|
|
}
|
|
/* Setup HT1000 SouthBridge Controller - Single Channel Only */
|
|
else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
|
|
pci_read_config_byte(dev, 0x5A, &btr);
|
|
btr &= ~0x40;
|
|
btr |= 0x3;
|
|
pci_write_config_byte(dev, 0x5A, btr);
|
|
}
|
|
|
|
return dev->irq;
|
|
}
|
|
|
|
static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
|
|
* of the subsystem device ID indicate presence of an 80-pin cable.
|
|
* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
|
|
* Bit 15 set = secondary IDE channel has 80-pin cable.
|
|
* Bit 14 clear = primary IDE channel does not have 80-pin cable.
|
|
* Bit 14 set = primary IDE channel has 80-pin cable.
|
|
*/
|
|
static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
|
|
{
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
|
|
dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
|
|
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
|
|
dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
|
|
return ((1 << (hwif->channel + 14)) &
|
|
dev->subsystem_device) ? 1 : 0;
|
|
return 0;
|
|
}
|
|
|
|
/* Sun Cobalt Alpine hardware avoids the 80-pin cable
|
|
* detect issue by attaching the drives directly to the board.
|
|
* This check follows the Dell precedent (how scary is that?!)
|
|
*
|
|
* WARNING: this only works on Alpine hardware!
|
|
*/
|
|
static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
|
|
{
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
|
|
dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
|
|
dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
|
|
return ((1 << (hwif->channel + 14)) &
|
|
dev->subsystem_device) ? 1 : 0;
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
|
|
{
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
|
|
/* Server Works */
|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
|
|
return ata66_svwks_svwks (hwif);
|
|
|
|
/* Dell PowerEdge */
|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
|
|
return ata66_svwks_dell (hwif);
|
|
|
|
/* Cobalt Alpine */
|
|
if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
|
|
return ata66_svwks_cobalt (hwif);
|
|
|
|
/* Per Specified Design by OEM, and ASIC Architect */
|
|
if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
|
|
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
|
|
{
|
|
u8 dma_stat = 0;
|
|
|
|
if (!hwif->irq)
|
|
hwif->irq = hwif->channel ? 15 : 14;
|
|
|
|
hwif->tuneproc = &svwks_tune_drive;
|
|
hwif->speedproc = &svwks_tune_chipset;
|
|
|
|
hwif->atapi_dma = 1;
|
|
|
|
if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
|
|
hwif->ultra_mask = 0x3f;
|
|
|
|
hwif->mwdma_mask = 0x07;
|
|
|
|
hwif->autodma = 0;
|
|
|
|
if (!hwif->dma_base) {
|
|
hwif->drives[0].autotune = 1;
|
|
hwif->drives[1].autotune = 1;
|
|
return;
|
|
}
|
|
|
|
hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
|
|
if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
|
|
hwif->ide_dma_end = &svwks_ide_dma_end;
|
|
else if (!(hwif->udma_four))
|
|
hwif->udma_four = ata66_svwks(hwif);
|
|
if (!noautodma)
|
|
hwif->autodma = 1;
|
|
|
|
dma_stat = hwif->INB(hwif->dma_status);
|
|
hwif->drives[0].autodma = (dma_stat & 0x20);
|
|
hwif->drives[1].autodma = (dma_stat & 0x40);
|
|
hwif->drives[0].autotune = (!(dma_stat & 0x20));
|
|
hwif->drives[1].autotune = (!(dma_stat & 0x40));
|
|
}
|
|
|
|
/*
|
|
* We allow the BM-DMA driver to only work on enabled interfaces.
|
|
*/
|
|
static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
|
|
{
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
|
|
if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
|
|
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
|
|
(!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
|
|
return;
|
|
|
|
ide_setup_dma(hwif, dmabase, 8);
|
|
}
|
|
|
|
static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
|
|
{
|
|
return ide_setup_pci_device(dev, d);
|
|
}
|
|
|
|
static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
|
|
{
|
|
if (!(PCI_FUNC(dev->devfn) & 1)) {
|
|
d->bootable = NEVER_BOARD;
|
|
if (dev->resource[0].start == 0x01f1)
|
|
d->bootable = ON_BOARD;
|
|
}
|
|
|
|
d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
|
|
dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
|
|
(!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
|
|
|
|
return ide_setup_pci_device(dev, d);
|
|
}
|
|
|
|
static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
|
|
{ /* 0 */
|
|
.name = "SvrWks OSB4",
|
|
.init_setup = init_setup_svwks,
|
|
.init_chipset = init_chipset_svwks,
|
|
.init_hwif = init_hwif_svwks,
|
|
.channels = 2,
|
|
.autodma = AUTODMA,
|
|
.bootable = ON_BOARD,
|
|
},{ /* 1 */
|
|
.name = "SvrWks CSB5",
|
|
.init_setup = init_setup_svwks,
|
|
.init_chipset = init_chipset_svwks,
|
|
.init_hwif = init_hwif_svwks,
|
|
.init_dma = init_dma_svwks,
|
|
.channels = 2,
|
|
.autodma = AUTODMA,
|
|
.bootable = ON_BOARD,
|
|
},{ /* 2 */
|
|
.name = "SvrWks CSB6",
|
|
.init_setup = init_setup_csb6,
|
|
.init_chipset = init_chipset_svwks,
|
|
.init_hwif = init_hwif_svwks,
|
|
.init_dma = init_dma_svwks,
|
|
.channels = 2,
|
|
.autodma = AUTODMA,
|
|
.bootable = ON_BOARD,
|
|
},{ /* 3 */
|
|
.name = "SvrWks CSB6",
|
|
.init_setup = init_setup_csb6,
|
|
.init_chipset = init_chipset_svwks,
|
|
.init_hwif = init_hwif_svwks,
|
|
.init_dma = init_dma_svwks,
|
|
.channels = 1, /* 2 */
|
|
.autodma = AUTODMA,
|
|
.bootable = ON_BOARD,
|
|
},{ /* 4 */
|
|
.name = "SvrWks HT1000",
|
|
.init_setup = init_setup_svwks,
|
|
.init_chipset = init_chipset_svwks,
|
|
.init_hwif = init_hwif_svwks,
|
|
.init_dma = init_dma_svwks,
|
|
.channels = 1, /* 2 */
|
|
.autodma = AUTODMA,
|
|
.bootable = ON_BOARD,
|
|
}
|
|
};
|
|
|
|
/**
|
|
* svwks_init_one - called when a OSB/CSB is found
|
|
* @dev: the svwks device
|
|
* @id: the matching pci id
|
|
*
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
|
* finds a device matching our IDE device tables.
|
|
*/
|
|
|
|
static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
|
|
|
|
return d->init_setup(dev, d);
|
|
}
|
|
|
|
static struct pci_device_id svwks_pci_tbl[] = {
|
|
{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
|
{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
|
|
{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
|
|
{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
|
|
{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "Serverworks_IDE",
|
|
.id_table = svwks_pci_tbl,
|
|
.probe = svwks_init_one,
|
|
};
|
|
|
|
static int svwks_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(svwks_ide_init);
|
|
|
|
MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
|
|
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
|
|
MODULE_LICENSE("GPL");
|