f1f5465782
The A0 revision of the mv78xx0 development board has four ethernet ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY addresses 8-9. This patch configures the third and fourth ethernet port to use the PHY addresses on the A0 board to enable use of those ports -- if we are running on a Z0 board, the ge10/11 setup code in common.c will force these back to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> |
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| .. | ||
| include/mach | ||
| addr-map.c | ||
| common.c | ||
| common.h | ||
| db78x00-bp-setup.c | ||
| irq.c | ||
| Kconfig | ||
| Makefile | ||
| Makefile.boot | ||
| pcie.c | ||